Can I Pass a 2D Array as a Parameter to a Procedure?

[Chris]

Hi All

I have an array of seven 32-bit std_logic registers, and I am trying to use
this array as an OUT parameter in a procedure. When I do so, Modelsim gives
me a "No feasible entries for subprogram" error.

Is it possible to pass a 2-dimensional array to a procedure, and if so, how?

Thanks,
Chris

 

[Chris]

I worded the above poorly. VHDL has no 2D arrays - I should have said an
array of arrays.

"Chris" <chris@skymicro.net> wrote in message
newsOWdne8C1oY0HxjbnZ2dnUVZ_uygnZ2d@comcast.com...

Hi All

I have an array of seven 32-bit std_logic registers, and I am trying to
use this array as an OUT parameter in a procedure. When I do so, Modelsim
gives me a "No feasible entries for subprogram" error.

Is it possible to pass a 2-dimensional array to a procedure, and if so,
how?

Thanks,
Chris

 

[Jonathan Bromley]

On Fri, 29 Jun 2007 15:36:42 -0700, "Chris" <chris@skymicro.net>
wrote:

I worded the above poorly. VHDL has no 2D arrays - I should have said an
array of arrays.

VHDL *does* have true N-dimensional arrays, but in practice
they are less useful than you might hope.

I have an array of seven 32-bit std_logic registers, and I am trying to
use this array as an OUT parameter in a procedure. When I do so, Modelsim
gives me a "No feasible entries for subprogram" error.

I don't really see why this should be a problem...

subtype SLV32 is std_logic_vector(31 downto 0);
type A_SLV32 is array(natural range <&gt of SLV32;
--- you need these types to be in a package so that
--- they can be imported anywhere with "use"
....
procedure twiddle(
A: in A_SLV32;
Y: out A_SLV32
) is
begin
-- confirm arrays are the same shape
assert (A'left = Y'left) and (A'right = Y'right);
for i in A'range loop
Y(i) := some_function_of(A(i));
end loop;
end;

....

variable P, Q: A_SLV32(1 to 4);
....
twiddle(P, Q);

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Chris]

Hi Jonathan

Sorry for the late reply - I got shifted onto another ultra-urgent (aren't
they always) task and haven't had time to look at this till now. What you're
advising looks like what I'm doing already, but I'll take a look and see if
I can spot what I'm doing wrong.

Thanks,
Chris

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:5u5c83pjoi1vcpnjh99vm6109i0lb43ekh@4ax.com...

On Fri, 29 Jun 2007 15:36:42 -0700, "Chris" <chris@skymicro.net
wrote:

I worded the above poorly. VHDL has no 2D arrays - I should have said an
array of arrays.

VHDL *does* have true N-dimensional arrays, but in practice
they are less useful than you might hope.

I have an array of seven 32-bit std_logic registers, and I am trying to
use this array as an OUT parameter in a procedure. When I do so,
Modelsim
gives me a "No feasible entries for subprogram" error.

I don't really see why this should be a problem...

subtype SLV32 is std_logic_vector(31 downto 0);
type A_SLV32 is array(natural range <&gt of SLV32;
--- you need these types to be in a package so that
--- they can be imported anywhere with "use"
...
procedure twiddle(
A: in A_SLV32;
Y: out A_SLV32
) is
begin
-- confirm arrays are the same shape
assert (A'left = Y'left) and (A'right = Y'right);
for i in A'range loop
Y(i) := some_function_of(A(i));
end loop;
end;

...

variable P, Q: A_SLV32(1 to 4);
...
twiddle(P, Q);

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Chris wrote:

I worded the above poorly. VHDL has no 2D arrays - I should have said an
array of arrays.

See the register stack source here:
http://home.comcast.net/~mike_treseler/
for an array of vectors example.

The push and pop operations could be parameterized.

-- Mike Treseler