can i increase da simulation speed of design

[anupam]

Hi everybody,
can I increase the simulation speed of my designs . I am using ModelSim
Altera version 5.8c

Thanx in advance.

Anupam

 

[anupam]

I am working with VHDL code for multichannel HDLC.
Regards,
Anupam

 

[Mike Treseler]

anupam wrote:

can I increase the simulation speed of my designs . I am using ModelSim
Altera version 5.8c I am working with VHDL code for multichannel HDLC.

Simulation of source code runs about
ten times faster than simulation of
a netlist.

-- Mike Treseler

 

[Allan Herriman]

On Fri, 03 Sep 2004 06:32:15 -0700, Mike Treseler
<mike_treseler@comcast.net> wrote:

anupam wrote:
can I increase the simulation speed of my designs . I am using ModelSim
Altera version 5.8c I am working with VHDL code for multichannel HDLC.

Simulation of source code runs about
ten times faster than simulation of
a netlist.

My source code often has lots of low level library primitives (e.g.
from Xilinx's Unisim library) and these are very slow. Replacing them
with behavioural models (with no timing checks, etc.) typically
improves simulation speed by 2-3 times.

The basic rule is: the higher the level of abstraction, the faster the
simulation.

Regards,
Allan