can I convert DPRAM to SPRAM?

[vlsifresher]

Hi,

Is there any way of implementing a DPRAM from single port RAM(may be
by connecting two SPRAM's)?

Thanks

 

[John_H]

vlsi_learner wrote:

Hi,

Is there any way of implementing DPRAM from single port RAM's?(may be
by connecting two SPRAM's)

Thanks

Maybe.

Do you have extra clock cycles available to do multiple reads and writes
in one memory and make it "look" like a mult-port memory?

Is you SPRAM truly only one address? There are "pseudo" dual-port
memories and "true" dual port memories. A true dual port can be made
from 2 pseudo dual ports.

So. What is the structure of your SPRAM? What DPRAM structure do you
want? What is your operating frequency versus maximum memory frequency?
Are you targeting a specific device?

 

[vlsifresher]

Hi John,

My SPRAM will have only one address.The DPRAM needs to be such that I
will only write through portA & only read through port B.

On Feb 20, 6:28 am, John_H <newsgr...@johnhandwork.com> wrote:

vlsi_learner wrote:
Hi,

Is there any way of implementing DPRAM from single port RAM's?(may be
by connecting two SPRAM's)

Thanks

Maybe.

Do you have extra clock cycles available to do multiple reads and writes
in one memory and make it "look" like a mult-port memory?

Is you SPRAM truly only one address? There are "pseudo" dual-port
memories and "true" dual port memories. A true dual port can be made
from 2 pseudo dual ports.

So. What is the structure of your SPRAM? What DPRAM structure do you
want? What is your operating frequency versus maximum memory frequency?
Are you targeting a specific device?

 

[John_H]

And I'll repeat the other questions:

What is your operating frequency versus maximum memory frequency?
If you have a 50 MHz read/write clock and your memory can give you 300 MHz
performance, you can use a faster clock and time multiplex your writes and
reads.
Are you targeting a specific device?
If you don't know the device capabilities but have a specific FPGA or ASIC
in mind, perhaps you could get specific help from those who know your target
well.

If this is just a homework problem - no specific device, no specific
frequency - be up front about it and you're more likely to get good help.

- John_H


"vlsifresher" <bajajk@gmail.com> wrote in message
news:1171986778.256284.152970@q2g2000cwa.googlegroups.com...

Hi John,

My SPRAM will have only one address.The DPRAM needs to be such that I
will only write through portA & only read through port B.

On Feb 20, 6:28 am, John_H <newsgr...@johnhandwork.com> wrote:
vlsi_learner wrote:
Hi,

Is there any way of implementing DPRAM from single port RAM's?(may be
by connecting two SPRAM's)

Thanks

Maybe.

Do you have extra clock cycles available to do multiple reads and writes
in one memory and make it "look" like a mult-port memory?

Is you SPRAM truly only one address? There are "pseudo" dual-port
memories and "true" dual port memories. A true dual port can be made
from 2 pseudo dual ports.

So. What is the structure of your SPRAM? What DPRAM structure do you
want? What is your operating frequency versus maximum memory frequency?
Are you targeting a specific device?

 

[vlsifresher]

My writes take place at 60 Mhz & reads at 35 Mhz.
The maxm memory freq is 120 Mhz.
I require it for an ASIC design

Thanks

On Feb 20, 10:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

And I'll repeat the other questions:

What is your operating frequency versus maximum memory frequency?
If you have a 50 MHz read/write clock and your memory can give you 300 MHz
performance, you can use a faster clock and time multiplex your writes and
reads.
Are you targeting a specific device?
If you don't know the device capabilities but have a specific FPGA or ASIC
in mind, perhaps you could get specific help from those who know your target
well.

If this is just a homework problem - no specific device, no specific
frequency - be up front about it and you're more likely to get good help.

- John_H

"vlsifresher" <baj...@gmail.com> wrote in message

news:1171986778.256284.152970@q2g2000cwa.googlegroups.com...

Hi John,

My SPRAM will have only one address.The DPRAM needs to be such that I
will only write through portA & only read through port B.

On Feb 20, 6:28 am, John_H <newsgr...@johnhandwork.com> wrote:
vlsi_learner wrote:
Hi,

Is there any way of implementing DPRAM from single port RAM's?(may be
by connecting two SPRAM's)

Thanks

Maybe.

Do you have extra clock cycles available to do multiple reads and writes
in one memory and make it "look" like a mult-port memory?

Is you SPRAM truly only one address? There are "pseudo" dual-port
memories and "true" dual port memories. A true dual port can be made
from 2 pseudo dual ports.

So. What is the structure of your SPRAM? What DPRAM structure do you
want? What is your operating frequency versus maximum memory frequency?
Are you targeting a specific device?

 

[John_H]

Doesn't the ASIC library have dual-port RAMs? As I said, if you have a
target ASIC in mind, perhaps those that have used that ASIC can help.
You can probably use a dual-port library element directly.

If a single port truly is all you have available, run the memory at a
higher frequency and perform the reads and writes as time-muliplexed
operations. The asynchronous write/read time domains makes the
coordination a pain in the neck but it's doable. If you need a read
valid shortly after a write, you may need additional logic to allow that
turnaround to occur quickly.

It's not pretty but it's doable with just single port SRAMs. First,
look for native pseudo dual port memories from the ASIC vendor. Only if
that fails, use a fast clock preferably at 3x the read clock where you
can have the read transaction occur as if it's real time and use posted
writes from that asynchronous time domain.


vlsifresher wrote:

My writes take place at 60 Mhz & reads at 35 Mhz.
The maxm memory freq is 120 Mhz.
I require it for an ASIC design

Thanks

On Feb 20, 10:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
And I'll repeat the other questions:

What is your operating frequency versus maximum memory frequency?
If you have a 50 MHz read/write clock and your memory can give you 300 MHz
performance, you can use a faster clock and time multiplex your writes and
reads.
Are you targeting a specific device?
If you don't know the device capabilities but have a specific FPGA or ASIC
in mind, perhaps you could get specific help from those who know your target
well.

If this is just a homework problem - no specific device, no specific
frequency - be up front about it and you're more likely to get good help.

- John_H