Can anyone explain me this code...

[dipesh.trivedi]

Hi friends,

i am having some problem in understanding this code... its a part of
memory model code of samsung. here it is,

if ( add_ptr == `H00 && add_ptr == `H50 && add_ptr == `H01)
begin
if (rbb == `BUSY)
begin
add_ptr = `H00;
com_com = `H00;
#1 faddr[8] = 1'b0;
out_reg = `HIZ;
end
end
can we write like this?????????????
if yes what does it mean? i am totally blank. as i have not much
experience with verilog...
i hope some of you will be knowing what it is... please help me out if
you understand this code...

Dipesh.

 

[Michael]

Please find definitions of "H00","H50" and "H01". What do you see
there?
dipesh.trivedi wrote:

Hi friends,

i am having some problem in understanding this code... its a part of
memory model code of samsung. here it is,

if ( add_ptr == `H00 && add_ptr == `H50 && add_ptr == `H01)
begin
if (rbb == `BUSY)
begin
add_ptr = `H00;
com_com = `H00;
#1 faddr[8] = 1'b0;
out_reg = `HIZ;
end
end
can we write like this?????????????
if yes what does it mean? i am totally blank. as i have not much
experience with verilog...
i hope some of you will be knowing what it is... please help me out if
you understand this code...

Dipesh.

 

[ABC]

Hi Dipesh,
Are you blank because of the following line?
if ( add_ptr == `H00 && add_ptr == `H50 && add_ptr == `H01)
Is `H00==`H50==`H01?
else, this if loop will be skip.
I don't know why it is code like this either.

Best regards,
ABC

dipesh.trivedi wrote:

Hi friends,

i am having some problem in understanding this code... its a part of
memory model code of samsung. here it is,

if ( add_ptr == `H00 && add_ptr == `H50 && add_ptr == `H01)
begin
if (rbb == `BUSY)
begin
add_ptr = `H00;
com_com = `H00;
#1 faddr[8] = 1'b0;
out_reg = `HIZ;
end
end
can we write like this?????????????
if yes what does it mean? i am totally blank. as i have not much
experience with verilog...
i hope some of you will be knowing what it is... please help me out if
you understand this code...

Dipesh.

 

[ajjc]

Hmmm...
Looked this up in Palnitkar's book "Verilog HDL", Section 6.4.2, and
'H00, 'H50, and 'H01 are, by default hex values for a 32-bit quantity,
so addr_ptr could have x or z in it, which would make the conditionals
eval to x(ambiguous), but even with that, I don't see how one can get a
"logical-1" out of the conditional in the if (<expression&gt, which is
what is needed to execute the "true_statement".

alan

 

[John_H]

The original poster suggested values of `H00, `H50, and `H01 which are
distinctly different than 'H00, 'H50, and 'H01. The `define for these
values are not shown in the code. Of course the original poster could have
mixed up his 's and `s.

"ajjc" <ajjc@optngn.com> wrote in message
news:1154619856.810140.166000@i42g2000cwa.googlegroups.com...

Hmmm...
Looked this up in Palnitkar's book "Verilog HDL", Section 6.4.2, and
'H00, 'H50, and 'H01 are, by default hex values for a 32-bit quantity,
so addr_ptr could have x or z in it, which would make the conditionals
eval to x(ambiguous), but even with that, I don't see how one can get a
"logical-1" out of the conditional in the if (<expression&gt, which is
what is needed to execute the "true_statement".

alan

 

[ajjc]

Oops!
You are right! Those are named define includes that start with a "`",
not constant
definition "'" marks. Makes sense now...just look up the definitions
to see what
values they have...as the first answerer suggested...good catch!
alan


John_H wrote:

The original poster suggested values of `H00, `H50, and `H01 which are
distinctly different than 'H00, 'H50, and 'H01. The `define for these
values are not shown in the code. Of course the original poster could have
mixed up his 's and `s.

"ajjc" <ajjc@optngn.com> wrote in message
news:1154619856.810140.166000@i42g2000cwa.googlegroups.com...
Hmmm...
Looked this up in Palnitkar's book "Verilog HDL", Section 6.4.2, and
'H00, 'H50, and 'H01 are, by default hex values for a 32-bit quantity,
so addr_ptr could have x or z in it, which would make the conditionals
eval to x(ambiguous), but even with that, I don't see how one can get a
"logical-1" out of the conditional in the if (<expression&gt, which is
what is needed to execute the "true_statement".

alan