Can anyone explain how a ser-par in verilog works?

C

Carlos Barberis

Guest
As you can see I am fairly new to the verilog hdl, I have been trying to
create a small functional module using an altera Max7000 series CPLD to take
in a 16 bit serial stream and convert it to a 16 bit parallel out. I have
checked my input serial stream with a logic analyzer and my data reads
correctly and all control signals are in their proper place, however my
parallel conversion in the CPLD always comes out incorrect; I am sending out
a 16 bit serial data word MSB first, when I send in a 0b0000000000000001 (1)
I see a 0b0000000000000011 (3) when I send a: 0b0000000000000010 (2) I see a
0b0000000000001100 (12) when I send a: 0b0000000000000011 (3)
I see a: 0b0000000000001111 (15)....and so on.

***************************** This is my verilog code
*****************************************************

module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock,
reset_n);

parameter SIZE = 16;
output[SIZE-1:0] parallel_out;
input serial_in;
input shift_enable;
input clock;
input reset_n;

reg[SIZE-1:0] tempdata;
reg[SIZE-1:0] parallel_out;

always @(posedge clock or negedge reset_n) begin
if (~reset_n)
tempdata <= 0;
else if(~shift_enable)
tempdata <= {tempdata[SIZE-2:0],serial_in};
parallel_out = tempdata;
end
endmodule
******************************************************************************************************
I tried changing; tempdata <= {tempdata[SIZE-1:1],serial_in}; but when I
do this the only thing I see in parallel_out is just the lsb turning on and
off for odd values
Any help or hints would be greatly appreciated.......Thank you!
 
Thank for your help Alex,
No I am not a VHDL user, however I did try it out previously without the
tempdata just using exactly what you describe -> parallel_out <=
{parallel_out[SIZE-2:0],serial_in};
I got the same results with that too,
I see what you mean about a blocking assignment, I guess that should be;
parallel_out <= tempdata;


"LittleAlex" <alex.louie@email.com> wrote in message
news:c4fb76a3-ca87-4ce6-9611-0ccb1c51f804@r36g2000prf.googlegroups.com...
On Oct 31, 8:14 am, "Carlos Barberis" <car...@bartek.com> wrote:
As you can see I am fairly new to the verilog hdl, I have been trying to
create a small functional module using an altera Max7000 series CPLD to
take
in a 16 bit serial stream and convert it to a 16 bit parallel out. I have
checked my input serial stream with a logic analyzer and my data reads
correctly and all control signals are in their proper place, however my
parallel conversion in the CPLD always comes out incorrect; I am sending
out
a 16 bit serial data word MSB first, when I send in a 0b0000000000000001
(1)
I see a 0b0000000000000011 (3) when I send a: 0b0000000000000010 (2) I
see a
0b0000000000001100 (12) when I send a: 0b0000000000000011 (3)
I see a: 0b0000000000001111 (15)....and so on.

***************************** This is my verilog code
*****************************************************

module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock,
reset_n);

parameter SIZE = 16;
output[SIZE-1:0] parallel_out;
input serial_in;
input shift_enable;
input clock;
input reset_n;

reg[SIZE-1:0] tempdata;
reg[SIZE-1:0] parallel_out;

always @(posedge clock or negedge reset_n) begin
if (~reset_n)
tempdata <= 0;
else if(~shift_enable)
tempdata <= {tempdata[SIZE-2:0],serial_in};
parallel_out = tempdata;
end
endmodule
******************************************************************************************************
I tried changing; tempdata <= {tempdata[SIZE-1:1],serial_in}; but when
I
do this the only thing I see in parallel_out is just the lsb turning on
and
off for odd values
Any help or hints would be greatly appreciated.......Thank you!

Are you a VHDL user learning Verilog? A blocking assign in a clocked
process is a no-no.

Get rid of tempdata and code it this way:
parallel_out <= {parallel_out[SIZE-2:0],serial_in};

Alex.
Click to expand...
 
On Oct 31, 8:14 am, "Carlos Barberis" <car...@bartek.com> wrote:
As you can see I am fairly new to the verilog hdl, I have been trying to
create a small functional module using an altera Max7000 series CPLD to take
in a 16 bit serial stream and convert it to a 16 bit parallel out. I have
checked my input serial stream with a logic analyzer and my data reads
correctly and all control signals are in their proper place, however my
parallel conversion in the CPLD always comes out incorrect; I am sending out
a 16 bit serial data word MSB first, when I send in a 0b0000000000000001 (1)
I see a 0b0000000000000011 (3) when I send a: 0b0000000000000010 (2) I see a
0b0000000000001100 (12) when I send a: 0b0000000000000011 (3)
I see a: 0b0000000000001111 (15)....and so on.

***************************** This is my verilog code
*****************************************************

module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock,
reset_n);

parameter SIZE = 16;
output[SIZE-1:0] parallel_out;
input serial_in;
input shift_enable;
input clock;
input reset_n;

reg[SIZE-1:0] tempdata;
reg[SIZE-1:0] parallel_out;

always @(posedge clock or negedge reset_n) begin
if (~reset_n)
tempdata <= 0;
else if(~shift_enable)
tempdata <= {tempdata[SIZE-2:0],serial_in};
parallel_out = tempdata;
end
endmodule
******************************************************************************************************
I tried changing; tempdata <= {tempdata[SIZE-1:1],serial_in}; but when I
do this the only thing I see in parallel_out is just the lsb turning on and
off for odd values
Any help or hints would be greatly appreciated.......Thank you!
Click to expand...
Are you a VHDL user learning Verilog? A blocking assign in a clocked
process is a no-no.

Get rid of tempdata and code it this way:
parallel_out <= {parallel_out[SIZE-2:0],serial_in};

Alex.
 
Carlos Barberis wrote:
Thank for your help Alex,
No I am not a VHDL user, however I did try it out previously without the
tempdata just using exactly what you describe -> parallel_out <=
{parallel_out[SIZE-2:0],serial_in};
I got the same results with that too,
I see what you mean about a blocking assignment, I guess that should be;
parallel_out <= tempdata;


"LittleAlex" <alex.louie@email.com> wrote in message
news:c4fb76a3-ca87-4ce6-9611-0ccb1c51f804@r36g2000prf.googlegroups.com...
On Oct 31, 8:14 am, "Carlos Barberis" <car...@bartek.com> wrote:
As you can see I am fairly new to the verilog hdl, I have been trying to
create a small functional module using an altera Max7000 series CPLD to
take
in a 16 bit serial stream and convert it to a 16 bit parallel out. I have
checked my input serial stream with a logic analyzer and my data reads
correctly and all control signals are in their proper place, however my
parallel conversion in the CPLD always comes out incorrect; I am sending
out
a 16 bit serial data word MSB first, when I send in a 0b0000000000000001
(1)
I see a 0b0000000000000011 (3) when I send a: 0b0000000000000010 (2) I
see a
0b0000000000001100 (12) when I send a: 0b0000000000000011 (3)
I see a: 0b0000000000001111 (15)....and so on.

***************************** This is my verilog code
*****************************************************

module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock,
reset_n);

parameter SIZE = 16;
output[SIZE-1:0] parallel_out;
input serial_in;
input shift_enable;
input clock;
input reset_n;

reg[SIZE-1:0] tempdata;
reg[SIZE-1:0] parallel_out;

always @(posedge clock or negedge reset_n) begin
if (~reset_n)
tempdata <= 0;
else if(~shift_enable)
tempdata <= {tempdata[SIZE-2:0],serial_in};
parallel_out = tempdata;
end
endmodule
******************************************************************************************************
I tried changing; tempdata <= {tempdata[SIZE-1:1],serial_in}; but when
I
do this the only thing I see in parallel_out is just the lsb turning on
and
off for odd values
Any help or hints would be greatly appreciated.......Thank you!

Are you a VHDL user learning Verilog? A blocking assign in a clocked
process is a no-no.

Get rid of tempdata and code it this way:
parallel_out <= {parallel_out[SIZE-2:0],serial_in};

Alex.
Click to expand...
Are you sure you want ~shift_enable? That will enable the if
statement when shift_enable is low, not high. If it's an active-low
signal, it's much more effective to use the signal name shift_enable_n
just like your active-low reset is called reset_n.

I've seen people use tempdata=value; and my_reg<=temdata; but never
blocking/nonblocking the other way around. It's never good to mix
this stuff; if nothing else, it leads to confusion even if you know
what the synthesis or simulation will do.

- John_H
 
On Oct 31, 10:38 am, John_H <newsgr...@johnhandwork.com> wrote:
Carlos Barberis wrote:
Thank for your help Alex,
No I am not a VHDL user, however I did try it out previously without the
tempdata just using exactly what you describe ->  parallel_out <> > {parallel_out[SIZE-2:0],serial_in};
I got the same results with that too,
I see what you mean about a blocking assignment, I guess that should be;
parallel_out <= tempdata;

"LittleAlex" <alex.lo...@email.com> wrote in message
news:c4fb76a3-ca87-4ce6-9611-0ccb1c51f804@r36g2000prf.googlegroups.com....
On Oct 31, 8:14 am, "Carlos Barberis" <car...@bartek.com> wrote:
As you can see I am fairly new to the verilog hdl, I have been trying to
create a small functional module using an altera Max7000 series CPLD to
take
in a 16 bit serial stream and convert it to a 16 bit parallel out. I have
checked my input serial stream with a logic analyzer and my data reads
correctly and all control signals are in their proper place, however my
parallel conversion in the CPLD always comes out incorrect; I am sending
out
a 16 bit serial data word MSB first, when I send in a 0b0000000000000001
(1)
I see a 0b0000000000000011 (3) when I send a: 0b0000000000000010 (2) I
see a
0b0000000000001100 (12) when I send a: 0b0000000000000011 (3)
I see a: 0b0000000000001111 (15)....and so on.

***************************** This is my verilog code
*****************************************************

module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock,
reset_n);

   parameter SIZE = 16;
   output[SIZE-1:0] parallel_out;
   input                serial_in;
   input                shift_enable;
   input                clock;
   input                reset_n;

   reg[SIZE-1:0] tempdata;
   reg[SIZE-1:0] parallel_out;

   always @(posedge clock  or negedge reset_n) begin
       if (~reset_n)
       tempdata <= 0;
      else if(~shift_enable)
     tempdata <= {tempdata[SIZE-2:0],serial_in};
       parallel_out = tempdata;
   end
 endmodule
******************************************************************************************************
I tried changing;   tempdata <= {tempdata[SIZE-1:1],serial_in};  but when
I
do this the only thing I see in parallel_out  is just the lsb turning on
and
off for odd values
Any help or hints would be greatly appreciated.......Thank you!

Are you a VHDL user learning Verilog?  A blocking assign in a clocked
process is a no-no.

Get rid of tempdata and code it this way:
       parallel_out <= {parallel_out[SIZE-2:0],serial_in};

Alex.

Are you sure you want ~shift_enable?  That will enable the if
statement when shift_enable is low, not high.  If it's an active-low
signal, it's much more effective to use the signal name shift_enable_n
just like your active-low reset is called reset_n.

I've seen people use tempdata=value; and my_reg<=temdata; but never
blocking/nonblocking the other way around.  It's never good to mix
this stuff; if nothing else, it leads to confusion even if you know
what the synthesis or simulation will do.

- John_H
Click to expand...
Did you simulate this? It seems to simple to have problems
but you never know.

Assuming everything else is O.K., the fact that you are getting
2 shifts per clock seems to imply that you are either not using
the clock you think you are, or you have ringing on the falling
clock edge creating an additional rising clock edge in the
middle of the cycle. What is your clock source? How long
is the wire connecting it to your CPLD?

All I can think of...
 
On Nov 1, 5:07 am, gabor <ga...@alacron.com> wrote:
On Oct 31, 10:38 am, John_H <newsgr...@johnhandwork.com> wrote:





Carlos Barberis wrote:
Thank for your help Alex,
No I am not a VHDL user, however I did try it out previously without the
tempdata just using exactly what you describe ->  parallel_out <> > > {parallel_out[SIZE-2:0],serial_in};
I got the same results with that too,
I see what you mean about a blocking assignment, I guess that should be;
parallel_out <= tempdata;

"LittleAlex" <alex.lo...@email.com> wrote in message
news:c4fb76a3-ca87-4ce6-9611-0ccb1c51f804@r36g2000prf.googlegroups.com....
On Oct 31, 8:14 am, "Carlos Barberis" <car...@bartek.com> wrote:
As you can see I am fairly new to the verilog hdl, I have been trying to
create a small functional module using an altera Max7000 series CPLD to
take
in a 16 bit serial stream and convert it to a 16 bit parallel out. I have
checked my input serial stream with a logic analyzer and my data reads
correctly and all control signals are in their proper place, however my
parallel conversion in the CPLD always comes out incorrect; I am sending
out
a 16 bit serial data word MSB first, when I send in a 0b0000000000000001
(1)
I see a 0b0000000000000011 (3) when I send a: 0b0000000000000010 (2) I
see a
0b0000000000001100 (12) when I send a: 0b0000000000000011 (3)
I see a: 0b0000000000001111 (15)....and so on.

***************************** This is my verilog code
*****************************************************

module serial_to_parallel ( parallel_out, serial_in, shift_enable, clock,
reset_n);

   parameter SIZE = 16;
   output[SIZE-1:0] parallel_out;
   input                serial_in;
   input                shift_enable;
   input                clock;
   input                reset_n;

   reg[SIZE-1:0] tempdata;
   reg[SIZE-1:0] parallel_out;

   always @(posedge clock  or negedge reset_n) begin
       if (~reset_n)
       tempdata <= 0;
      else if(~shift_enable)
     tempdata <= {tempdata[SIZE-2:0],serial_in};
       parallel_out = tempdata;
   end
 endmodule
***************************************************************************­***************************
I tried changing;   tempdata <= {tempdata[SIZE-1:1],serial_in};  but when
I
do this the only thing I see in parallel_out  is just the lsb turning on
and
off for odd values
Any help or hints would be greatly appreciated.......Thank you!

Are you a VHDL user learning Verilog?  A blocking assign in a clocked
process is a no-no.

Get rid of tempdata and code it this way:
       parallel_out <= {parallel_out[SIZE-2:0],serial_in};

Alex.

Are you sure you want ~shift_enable?  That will enable the if
statement when shift_enable is low, not high.  If it's an active-low
signal, it's much more effective to use the signal name shift_enable_n
just like your active-low reset is called reset_n.

I've seen people use tempdata=value; and my_reg<=temdata; but never
blocking/nonblocking the other way around.  It's never good to mix
this stuff; if nothing else, it leads to confusion even if you know
what the synthesis or simulation will do.

- John_H

Did you simulate this?  It seems to simple to have problems
but you never know.

Assuming everything else is O.K., the fact that you are getting
2 shifts per clock seems to imply that you are either not using
the clock you think you are, or you have ringing on the falling
clock edge creating an additional rising clock edge in the
middle of the cycle.  What is your clock source?  How long
is the wire connecting it to your CPLD?

All I can think of...- Hide quoted text -

- Show quoted text -
Click to expand...
For me
1> tempdata is not required.
2> I will also use "parallel_out <{parallel_out[SIZE-2:0],serial_in}; "
3> I will also prefer to run one counter telling me 16 bits has been
stored and then generate valid parallel_out flag.
4> Hope you are generating "serial_in" to "serial_to_parallel" using
same clock line as connected to module clk input.
 
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