Can anyone explain \"cannot currently create a parameter of type\" compilation error message?...

K

Kevin Simonson

Guest
I\'ve written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left) has the same value as (right), and returns a logical zero otherwise. My code is:
Code: 
module ModGc ( result, left, right);
output result;
input  left, right;

typedef enum { L_NOT, L_NAND, L_NOR } GateType;

typedef struct packed
{ GateType gateTp;
   integer out;
   integer inLow;
   integer inHigh;
} LogGate;

localparam integer nmGates  = 4;
localparam integer poolSize = 6;
localparam LogGate specs [ nmGates:1]
wire               pool  [ poolSize:1];
genvar             ix;

initial
begin
  specs[ 1].gateTp = L_NOR ; specs[ 1].out = 4; specs[ 1].inLow = 2; specs[ 1].inHigh = 3;
  specs[ 2].gateTp = L_NOT ; specs[ 2].out = 5; specs[ 2].inLow = 4; specs[ 2].inHigh = 0;
  specs[ 3].gateTp = L_NAND; specs[ 3].out = 6; specs[ 3].inLow = 2; specs[ 3].inHigh = 3;
  specs[ 4].gateTp = L_NOR ; specs[ 4].out = 1; specs[ 4].inLow = 5; specs[ 4].inHigh = 6;
end
  
assign pool[ 2] = left;
assign pool[ 3] = right;
for (ix = 1; ix <= nmGates; ix = ix + 1)
  case (specs[ ix].gateTp)
    L_NOT
  : not ntx( pool[ specs[ ix].out], pool[ specs[ ix].inLow]);
    L_NAND
  : nand nax( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
    L_NOR
  : nor nox( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
  endcase
assign result = pool[ 1];

endmodule
Once again, I\'m fully aware that there\'s a much simpler way to design an Equals circuit than this; again this is a simplification of a problem I\'m having in more complex code. Anyhow, I run the Icarus simulator on this and get:
Code: 
D:\\Hf\\Verilog\\Unpacked\\Common>\\Icarus\\bin\\iverilog -g2009 -o ModGc.out ModGc.sv
ModGc.sv:16: sorry: cannot currently create a parameter of type \'LogGate\' which was defined at: ModGc.sv:7.
ModGc.sv:16: syntax error
ModGc.sv:16: error: syntax error localparam list.

D:\\Hf\\Verilog\\Unpacked\\Common>
Can anyone tell me why the simulator is balking at line 16, where local parameter (specs) is declared? Any information anyone can give me on these compilation errors would be greatly appreciated.
 
On Wednesday, September 16, 2020 at 9:25:45 PM UTC-4, Kevin Simonson wrote:
> I forgot to say that my code is in Verilog!

Not that there is anything wrong with asking here, but you might try asking in comp.lang.verilog too. None of these groups are overly active, but there are a few good posters in each of them. So ask around.

I\'m not a Verilog guy at all or I would try to answer. However, this question seems rather complex.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
 
On Wednesday, September 16, 2020 at 7:22:25 PM UTC-6, Kevin Simonson wrote:
I\'ve written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left) has the same value as (right), and returns a logical zero otherwise. My code is:
Code: 
module ModGc ( result, left, right);
output result;
input left, right;

typedef enum { L_NOT, L_NAND, L_NOR } GateType;

typedef struct packed
{ GateType gateTp;
integer out;
integer inLow;
integer inHigh;
} LogGate;

localparam integer nmGates = 4;
localparam integer poolSize = 6;
localparam LogGate specs [ nmGates:1]
wire pool [ poolSize:1];
genvar ix;

initial
begin
specs[ 1].gateTp = L_NOR ; specs[ 1].out = 4; specs[ 1].inLow = 2; specs[ 1].inHigh = 3;
specs[ 2].gateTp = L_NOT ; specs[ 2].out = 5; specs[ 2].inLow = 4; specs[ 2].inHigh = 0;
specs[ 3].gateTp = L_NAND; specs[ 3].out = 6; specs[ 3].inLow = 2; specs[ 3].inHigh = 3;
specs[ 4].gateTp = L_NOR ; specs[ 4].out = 1; specs[ 4].inLow = 5; specs[ 4].inHigh = 6;
end

assign pool[ 2] = left;
assign pool[ 3] = right;
for (ix = 1; ix <= nmGates; ix = ix + 1)
case (specs[ ix].gateTp)
L_NOT
: not ntx( pool[ specs[ ix].out], pool[ specs[ ix].inLow]);
L_NAND
: nand nax( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
L_NOR
: nor nox( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
endcase
assign result = pool[ 1];

endmodule
Once again, I\'m fully aware that there\'s a much simpler way to design an Equals circuit than this; again this is a simplification of a problem I\'m having in more complex code. Anyhow, I run the Icarus simulator on this and get:
Code: 
D:\\Hf\\Verilog\\Unpacked\\Common>\\Icarus\\bin\\iverilog -g2009 -o ModGc.out ModGc.sv
ModGc.sv:16: sorry: cannot currently create a parameter of type \'LogGate\' which was defined at: ModGc.sv:7.
ModGc.sv:16: syntax error
ModGc.sv:16: error: syntax error localparam list.

D:\\Hf\\Verilog\\Unpacked\\Common
Can anyone tell me why the simulator is balking at line 16, where local parameter (specs) is declared? Any information anyone can give me on these compilation errors would be greatly appreciated.
Click to expand...

I copied this into the stuff I\'m working on and ran it through VCS just to see if it compiles. It does if I remove the keyword \"localparam\" on the offending line 16. A parameter is a constant, in any case, and I don\'t think it can be modifed after it is declared. I didn\'t see if the code actually works, but it at least compiles if you remove that word.

I hope this is just for simulation, because synthesizers are not going to like a lot of this, such as the \"initial\" block, and may even balk at structures and enums.
 
On Thursday, September 17, 2020 at 1:44:49 PM UTC-4, Kevin Neilson wrote:
On Wednesday, September 16, 2020 at 7:22:25 PM UTC-6, Kevin Simonson wrote:
I\'ve written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left) has the same value as (right), and returns a logical zero otherwise. My code is:
Code: 
module ModGc ( result, left, right);
output result;
input left, right;

typedef enum { L_NOT, L_NAND, L_NOR } GateType;

typedef struct packed
{ GateType gateTp;
integer out;
integer inLow;
integer inHigh;
} LogGate;

localparam integer nmGates = 4;
localparam integer poolSize = 6;
localparam LogGate specs [ nmGates:1]
wire pool [ poolSize:1];
genvar ix;

initial
begin
specs[ 1].gateTp = L_NOR ; specs[ 1].out = 4; specs[ 1].inLow = 2; specs[ 1].inHigh = 3;
specs[ 2].gateTp = L_NOT ; specs[ 2].out = 5; specs[ 2].inLow = 4; specs[ 2].inHigh = 0;
specs[ 3].gateTp = L_NAND; specs[ 3].out = 6; specs[ 3].inLow = 2; specs[ 3].inHigh = 3;
specs[ 4].gateTp = L_NOR ; specs[ 4].out = 1; specs[ 4].inLow = 5; specs[ 4].inHigh = 6;
end

assign pool[ 2] = left;
assign pool[ 3] = right;
for (ix = 1; ix <= nmGates; ix = ix + 1)
case (specs[ ix].gateTp)
L_NOT
: not ntx( pool[ specs[ ix].out], pool[ specs[ ix].inLow]);
L_NAND
: nand nax( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
L_NOR
: nor nox( pool[ specs[ ix].out], pool[ specs[ ix].inLow], pool[ specs[ ix].inHigh]);
endcase
assign result = pool[ 1];

endmodule
Once again, I\'m fully aware that there\'s a much simpler way to design an Equals circuit than this; again this is a simplification of a problem I\'m having in more complex code. Anyhow, I run the Icarus simulator on this and get:
Code: 
D:\\Hf\\Verilog\\Unpacked\\Common>\\Icarus\\bin\\iverilog -g2009 -o ModGc.out ModGc.sv
ModGc.sv:16: sorry: cannot currently create a parameter of type \'LogGate\' which was defined at: ModGc.sv:7.
ModGc.sv:16: syntax error
ModGc.sv:16: error: syntax error localparam list.

D:\\Hf\\Verilog\\Unpacked\\Common
Can anyone tell me why the simulator is balking at line 16, where local parameter (specs) is declared? Any information anyone can give me on these compilation errors would be greatly appreciated.

I copied this into the stuff I\'m working on and ran it through VCS just to see if it compiles. It does if I remove the keyword \"localparam\" on the offending line 16. A parameter is a constant, in any case, and I don\'t think it can be modifed after it is declared. I didn\'t see if the code actually works, but it at least compiles if you remove that word.

I hope this is just for simulation, because synthesizers are not going to like a lot of this, such as the \"initial\" block, and may even balk at structures and enums.
Click to expand...

Why would synthesis balk at the initial block? I\'ve been looking at this and many document the fact that an intialization is the \"right\" way to specific the configuration start up state, although they don\'t use an initial block.

module top (q, d, clk, reset);
input d;
input clk;
input reset;
output q;
reg q_reg = 1\'b1;
always @(posedge clk)begin
if(reset)
q_reg<=1\'b0;
else
q_reg<=d;
end
assign q = q_reg;
endmodule

Durn indentation didn\'t copy so I had to fat finger it.

I don\'t really know Verilog, so I don\'t know the difference between using an initial block and the above initialization in the declaration.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
 
In article <b5898556-299c-4204-b316-e16d5c9b70b0n@googlegroups.com>,
Kevin Simonson <kvnsmnsn@hotmail.com> wrote:
I\'ve written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left)
has the same value as (right), and returns a logical zero otherwise. My code is:
Code: 
module ModGc ( result, left, right);
output result;
input  left, right;

typedef enum { L_NOT, L_NAND, L_NOR } GateType;

typedef struct packed
{ GateType gateTp;
integer out;
integer inLow;
integer inHigh;
} LogGate;

localparam integer nmGates  = 4;
localparam integer poolSize = 6;
localparam LogGate specs [ nmGates:1]
wire               pool  [ poolSize:1];
genvar             ix;

initial
begin
specs[ 1].gateTp = L_NOR ; specs[ 1].out = 4; specs[ 1].inLow = 2; specs[ 1].inHigh = 3;
specs[ 2].gateTp = L_NOT ; specs[ 2].out = 5; specs[ 2].inLow = 4; specs[ 2].inHigh = 0;
specs[ 3].gateTp = L_NAND; specs[ 3].out = 6; specs[ 3].inLow = 2; specs[ 3].inHigh = 3;
specs[ 4].gateTp = L_NOR ; specs[ 4].out = 1; specs[ 4].inLow = 5; specs[ 4].inHigh = 6;
end[/quote]

<snip>
localparms (and parameters) values can only be set during definition.  You
cannot modify them within a procedural block (initial block in your
case) as you\'ve shown.

There are tricks your can do if you want to use procedural code to
calculate parameter values.  But not within procedural blocks as you\'ve
done.

Regards,
Mark
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top