Can a function be synchronous?

[cruzin]

Is it possible to make a function synchronous to the clock?

I have written an arbitrary-size mux using a recursive function:

function mux( ... )
begin
...
return ( mux(top_half), mux(bottom_half) );
end mux;

To improve synthesized performance, I want to register each level of
the mux. Something like:

function mux( clk, ... )
begin
...
wait until clk='1';
return ( mux(top_half), mux(bottom_half) );
end mux;

I realize I can not use wait in a function.

Are functions always meant to complete in zero-time? Is my only
recourse to write the synchronous mux using a recursive component
model?

 

[Jim Lewis]

You are correct you cannot use wait in a function.

If you want to create a register in either a function
or procedure, I recommend using rising_edge:

architecture RTL of Shift4x1 is -- 4 Stage Shift Reg
procedure FF(
signal Clk : in Std_Logic ;
nReset : in Std_Logic ;
D : in Std_Logic ;
signal Q : out Std_Logic
) is
begin
if nReset='0' then
Q <= '0';
elsif Rising_Edge(Clk) then
Q <= D;
end if;
end FF;
-- Clk, nReset, D, Q are ports of std_logic
signal Reg1, Reg2, Reg3 ;
begin
FF(Clk, nReset, D, Reg1);
FF(Clk, nReset, Reg1, Reg2);
FF(Clk, nReset, Reg3, Q);
end RTL ;


Currently this may not be synthesizable in all
tools, but it should be in the future as it is
called for in 1076.6-200X.


Obviously this does not solve your recursion problem.
I cannot see a way to handle it with a procedure as
you would need to be able to create a signal to hold
intermediate values. As a result, I think your
only alternative is to have some fun with an entity
with a generic and generate.


This is not the way I would solve your problem though.
First to give the synthesis tool good control of
a multiplexer chain, I prefer to use and-or logic.
And-Or at the first level, and then it becomes OR
at the upper levels.

Next, if I have a timing problem, I would plan on
using the pipeline retiming capability of the
synthesis tool. Basically code N registers in
sequence after the multiplexer and allow the synthesis
tool to move them around as it sees fit.

This will also allow you to tune the number of
registers you need based on your timing, rather than
having a register following each multiplexer stage.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


cruzin wrote:

Is it possible to make a function synchronous to the clock?

I have written an arbitrary-size mux using a recursive function:

function mux( ... )
begin
...
return ( mux(top_half), mux(bottom_half) );
end mux;

To improve synthesized performance, I want to register each level of
the mux. Something like:

function mux( clk, ... )
begin
...
wait until clk='1';
return ( mux(top_half), mux(bottom_half) );
end mux;

I realize I can not use wait in a function.

Are functions always meant to complete in zero-time? Is my only
recourse to write the synchronous mux using a recursive component
model?

 

[Mike Treseler]

cruzin wrote:

Is it possible to make a function synchronous to the clock?

No. A function is a value calculation.
It is wires and gates, not flops.

To improve synthesized performance, I want to register each level of
the mux. Something like:

function mux( clk, ... )
begin
...
wait until clk='1';
return ( mux(top_half), mux(bottom_half) );
end mux;

I realize I can not use wait in a function.

The only wait you really need for
synthesis is

elsif rising_edge(clk) then

Consider calling a procedure from inside
a clocked process. Use a process variable
to keep track of the mux state.

-- Mike Treseler