can 2 if's to 1 if save 1 clock cycle?

[bxbxb3]

Hi,
I would like to ask if altering 1st code into 2nd would help save 1 clock
cycle.

1)process(clk)
begin
if(reset='1') then
xyz<="00";
else
if(clk'event and clk='1') then
xyz<="11";
:
:
:


2)process(clk)
begin
if(reset='1') then
xyz<="00";
elsif(reset='0' and (clk'event and clk='1')) then
xyz<="11";
:
:
:

Thanks!

 

[Jim George]

bxbxb3 wrote:

Hi,
I would like to ask if altering 1st code into 2nd would help save 1 clock
cycle.

1)process(clk)
begin
if(reset='1') then
xyz<="00";
else
if(clk'event and clk='1') then
xyz<="11";
:
:
:


2)process(clk)
begin
if(reset='1') then
xyz<="00";
elsif(reset='0' and (clk'event and clk='1')) then
xyz<="11";
:
:
:

Thanks!

Don't think of VHDL as a sequential language, in which statements
execute one after the other. All synthesizable statements in a vhdl
program synthesize into logic of some form, in your case it will form a
pair of registers (xyz<1> and xyz<0&gt which have an asynchronous reset
and both D inputs are connected to logic '1'. Both pieces of code do the
same thing, one is not more efficient than the other.
-Jim

 

[Mohammed A khader]

Hi ,

Both are functionally same. You cannot save any clock cycle here.

your sensitivity list is not complete , it must include reset since
it is outside the synchronous condition.

-- Mohammed A Khader.