Calling modules from Always block in VERILOG.

[shragafr]

Hello.

I wrote code in verilog that recieve serial data,convert it to parrallel
word and convert it from binary to bcd, and from bcd to 7 segment.

the "binary to bcd" and "bcd to 7 segment" are separete
modules (different .v files).
I tried to use them from ALWAYS block but the top module does'nt recognize
these modules.
when I get tese files out of the always loop the top module start
to "see"these files

Does anybody know the reasone for this???

thank in advance
shraga.

 

[Jason Rosinski]

The always blocks within the top level module specify logic created at that level of hierarchy.
i.e., flip flops, latches, combinatorial logic etc.

To create an instantiation of another design, you don't call it in an always block. You just
define it as an instantiation.

i.e.,

module my_top( clk, rst, data_in, out );
input clk;
input rst;
input data_in;
output out;

reg clked_rst;

my_submodule inst1( .clk(clk), .rst(clked_rst), .data(data_in), .q(out) );

always @(posedge clk) begin
clked_rst <= rst;
end

endmodule

Does this example make sense?

shragafr wrote:

Hello.

I wrote code in verilog that recieve serial data,convert it to parrallel
word and convert it from binary to bcd, and from bcd to 7 segment.

the "binary to bcd" and "bcd to 7 segment" are separete
modules (different .v files).
I tried to use them from ALWAYS block but the top module does'nt recognize
these modules.
when I get tese files out of the always loop the top module start
to "see"these files

Does anybody know the reasone for this???

thank in advance
shraga.

 

[shragafr]

Thank you for your answer.

I run your module on the "xillinx ISE 6" and after synthesize this
code I got the following messages:
..
..
..
..
=========================================================================

* HDL Analysis
*

=========================================================================

ERROR:HDLCompilers:246 - test.v line 9 Reference to scalar reg
'clked_rst' is not a legal net lvalue

ERROR:HDLCompilers:102 - test.v line 9 Connection to output port 'rst'
must be a net lvalue

-->
..
..
..


your source code was:

module my_top( clk, rst, data_in, out );

input clk;
input rst;
input data_in;
output out;
reg clked_rst;

line9: >>> my_submodule inst1( .clk(clk), .rst(clked_rst),
..data(data_in), .q(out) );

always @(posedge clk) begin
clked_rst <= rst;
end

Endmodule

In my experiences I got similar results, it seems that the
instantiation of another module can't output to register only to net.

Do you know how to get over on this problem???

 

[Jason Rosinski]

When you define the verilog for the submodule 'my_submodule', the 'rst' port has to be an input.
Otherwise it's trying to drive into a register, which isn't valid. I didn't include the verilog for
the submodule, since this is just an example.

If you just write an empty declaraction for the submodule, it should compile okay. i.e.,

module my_submodule( clk, rst, data, q);
input clk, rst, data;
output q;
endmodule


shragafr wrote:

Thank you for your answer.

I run your module on the "xillinx ISE 6" and after synthesize this
code I got the following messages:
.
.
.
.
=========================================================================

* HDL Analysis
*

=========================================================================

ERROR:HDLCompilers:246 - test.v line 9 Reference to scalar reg
'clked_rst' is not a legal net lvalue

ERROR:HDLCompilers:102 - test.v line 9 Connection to output port 'rst'
must be a net lvalue

--
.
.
.


your source code was:

module my_top( clk, rst, data_in, out );

input clk;
input rst;
input data_in;
output out;
reg clked_rst;

line9: >>> my_submodule inst1( .clk(clk), .rst(clked_rst),
.data(data_in), .q(out) );

always @(posedge clk) begin
clked_rst <= rst;
end

Endmodule

In my experiences I got similar results, it seems that the
instantiation of another module can't output to register only to net.

Do you know how to get over on this problem???