A
Andre
Guest
Dear all,
In VHDL it is possible to declare the following entity:
File Foo.vhd contains
entity Foo is
generic
(
Width : in natural := 3
);
port
(
Clock : in std_logic;
SIn : in std_logic
);
function Do_It return std_logic
end Foo;
Now I want to use this entity in Test.vhd
entity Test is
port ( .... )
architecture rtl of Test is
component Foo is
generic
(
Width : in natural := 3
);
port
(
Clock : in std_logic;
SIn : in std_logic
);
function Do_It return std_logic
end component;
begin
i_Foo : Foo
generic map
(
Width => 3
);
port map
(
Clock => Clk1,
SIn => Test
);
External <= Do_It; -- Error, unknown
end;
The question is (finally:
- How can I use the Do_It function in the other entity?
- If I can't, what is the use for the declaration part in an entity?
thanks,
André
In VHDL it is possible to declare the following entity:
File Foo.vhd contains
entity Foo is
generic
(
Width : in natural := 3
);
port
(
Clock : in std_logic;
SIn : in std_logic
);
function Do_It return std_logic
end Foo;
Now I want to use this entity in Test.vhd
entity Test is
port ( .... )
architecture rtl of Test is
component Foo is
generic
(
Width : in natural := 3
);
port
(
Clock : in std_logic;
SIn : in std_logic
);
function Do_It return std_logic
end component;
begin
i_Foo : Foo
generic map
(
Width => 3
);
port map
(
Clock => Clk1,
SIn => Test
);
External <= Do_It; -- Error, unknown
end;
The question is (finally:
- How can I use the Do_It function in the other entity?
- If I can't, what is the use for the declaration part in an entity?
thanks,
André