S
Shenli
Guest
Hi all,
Sometimes, I want to do some sophisticated text operation in Verilog or
SystemVerilog testbench. And we all know that Verilog and SV is like
C/C++ and not very good at text manipulation.
Is there any method to call Perl routine in Verilog or SV? Pass
argument to Perl routine can be better. BTW, I use Cadence NC tools.
Best regards,
Davy
Sometimes, I want to do some sophisticated text operation in Verilog or
SystemVerilog testbench. And we all know that Verilog and SV is like
C/C++ and not very good at text manipulation.
Is there any method to call Perl routine in Verilog or SV? Pass
argument to Perl routine can be better. BTW, I use Cadence NC tools.
Best regards,
Davy