calibre lvs issue

[Muzaffer Kal]

This is not a Cadence tool issue but I am hoping to present my problem
to a group potentially expert in this area.
The issue I'm facing is that calibre lvs is having difficulty
understanding some connectivity caused by port pass-thru in gate level
verilog. It's difficult to explain so let me give examples:

module top(clock, ...);
input clock;

CLKBUF buf(.A(clock), .Y(cb1));

u0 u0(.clock(clock), .cb1(cb1), .cb2(cb1)); // line 1

....
endmodule

module u0(clock, cb1, cb2...);
input clock, cb1, cb2;

DFF u0(.ck(clock)...);
DFF u1(.ck(cb1), ...);
DFF u2(.ck(cb2), ...);
endmodule

When I convert this to spice to run lvs I get

subckt top clock ...

Xbuf clock cb1 CLKBUF
Xu0 clock cb1 cb1 ...

ends

subckt u0 clock cb1 cb2 ...

Xu0 DFF clock ...
Xu1 DFF cb1 ...
Xu2 DFF cb2 ...

ends

When calibre sees this it gets vey confused. It gives connectivity
errors related to devices on net cb1 and cb2. Actually this problem is
relatively easy to fix. At 'line 1' commented line above, removing cb2
port and renaming all cb2 in u0 module to cb1 fixes it.
The more difficult problem is the 'clock' net. Calibrelvs thinks that
there are two nets in the source: 'clock' and 'u0/clock' but only one
corresponding net in layout. Obviously these are the same net but I
couldn't find any solution other than removing the 'clock' port in u0
and declaring 'clock' global to pass lvs. This is a solution I'd
rather not go with. Is there a way in calibre to pass lvs without
having to fix these net renaming issues ?

Thanks.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com