Calibre LVS errors

[Verictor]

Hi the Group,

As not an expert at all on LVS, I am having a whole bunch LVS errors
that seem very strange for me. The problem is:

We know this cell isn't LVS clean before hand. But we try to make the
final circuit LVS errors the same they are as an individual cell. Here
is what I have done:

1. Do Calibre LVS on the cell itself. I get property errors. Not
surprise.
2. Connect a simple circuit, e.g., an inverter to an output pin. Build
another layout from this schematic. Do LVS on this layout. The inverter
is LVS/DRC clean.
3. Now the errors increase in addition to the property errors in the
last step. From one of my co-worker's suggestion to understand what is
going on, I zoom into one error saying missing net in the problem cell
in Layout view. The net is there on the layout! I have no idea where it
is from.
4. Other LVS errors are hard to trace down too.

By the way, what are softcheck errors and stack errors in Calibre LVS
option setup?

I know this is not in detail at all. But any hint is highly
appreciated,

Thanks

 

[vlsidesign]

Here is some insight as I understand it:

Soft-connection errors check for "soft" connections. A soft-connection
is generally when two nets connect through the substrate (substrate is
basically everywhere that NWELL isn't that your NMOS device sits in.
Many times people have a 'soft-connection' between two different ground
supplies. So let say you have a nmos device with it's tiedown (guard
tie) that is tied to DVSS. This guard tie, ties the substrate, the
silicon, which your NMOS device sits in to the potential DVSS. Now if
you place another NMOS and tie it and it's guards to AVSS, you have a
'soft-connection' to each other that is connected through the
substrate. Usually, to fix this the devices are put in Deep nwell or
are double guard ringed with an NWELL guard tie and then another ring
of PSUB tie. This breaks up the substrate into pieces, although DNW
gives a more true isolation as compared to just NWELL ring.

Verictor wrote:

Hi the Group,

As not an expert at all on LVS, I am having a whole bunch LVS errors
that seem very strange for me. The problem is:

We know this cell isn't LVS clean before hand. But we try to make the
final circuit LVS errors the same they are as an individual cell. Here
is what I have done:

1. Do Calibre LVS on the cell itself. I get property errors. Not
surprise.
2. Connect a simple circuit, e.g., an inverter to an output pin. Build
another layout from this schematic. Do LVS on this layout. The inverter
is LVS/DRC clean.
3. Now the errors increase in addition to the property errors in the
last step. From one of my co-worker's suggestion to understand what is
going on, I zoom into one error saying missing net in the problem cell
in Layout view. The net is there on the layout! I have no idea where it
is from.
4. Other LVS errors are hard to trace down too.

By the way, what are softcheck errors and stack errors in Calibre LVS
option setup?

I know this is not in detail at all. But any hint is highly
appreciated,

Thanks