calculations of logic vectors and constant

[itay]

what is the prefered option of arithmetic operations using logic vector
and constant? convert logic vector to integer and do the operation or t
convert the constant to logic vector?

I have samples from A/D as logic vectors with some resolution an
constants. I want to do arithmetic operations between them according t
formula?
if anyone has examples of such thing it will be very helpfull (VHDL).



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Posted through http://www.FPGARelated.com

 

[Rob Gaddi]

On Mon, 18 Aug 2014 12:02:10 -0500
"itay" <101236@embeddedrelated> wrote:

what is the prefered option of arithmetic operations using logic vectors
and constant? convert logic vector to integer and do the operation or to
convert the constant to logic vector?

I have samples from A/D as logic vectors with some resolution and
constants. I want to do arithmetic operations between them according to
formula?
if anyone has examples of such thing it will be very helpfull (VHDL).



---------------------------------------
Posted through http://www.FPGARelated.com

std_logic_vectors don't do math. They only hold bits. If they're
doing math, you're using some library that you shouldn't be, like
std_logic_arith.

Unsigned/signed do in fact do math, and typecast from
std_logic_vector. You'll find them in numeric_std. They're useful for
doing math when you:
a) Need to be concerned about non-binary values such as 'X' and '-'
b) Specifically want the overflow rollover behavior on add/subtract
c) Have to deal with numbers outside the range +/-(2**31 - 1)

Integers are fundamentally better than unsigned/signed in simulation.
They're faster, you can ascribe specific bounds to them, and when you're
working with them they need less syntax (as opposed to getting in and
out of them, which is a whole other story). I prefer to use integers
where possible, and fall back to signed/unsigned for the above reasons
when I have to.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

On Monday, August 18, 2014 12:27:48 PM UTC-5, Rob Gaddi wrote:
> std_logic_vectors don't do math. They only hold bits. If they're doing math, you're using some library that you shouldn't be, like std_logic_arith.

As of the 2008 standard, the ieee.numeric_std_unsigned package extends arithmetic and relational operators, with an unsigned interpretation, to std_logic_vector. It also contains conversion functions for natural/std_logic_vector.

If you need signed arithmetic, then you need to use either numeric_std.signed. You can also use the ieee fixed point packages (sfixed type), with zero or more fractional bits. sfixed has the benefit of automatically expanding the result range/precision to handle the maximum/minimum arithmetic result, and can be configured for saturation and rounding logic on resize.

As for the use of integer or signed constants, my preference when defining a numerical value is to use integer if within integer'range. If using sfixed, then real constants are useful. Real/integer values can be added to sfixed/signed quantities automatically (the scalar operand is converted to signed/sfixed of same range/precision as the vector operand).

2008 also provides a floating point library in 2008, with configurably sized mantissa and exponent.

Andy