Calculating the average in Verilog...

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[smriti thakur]

hey follow this hope this can help

module Mean(in_n0,in_n1,in_n2,in_n3,out_mean);
input [3:0] in_n0,in_n1,in_n2,in_n3;
output reg [4:0] out_mean;
wire [5:0] w0,w1,w2,w3,sum;

assign w0={{2{in_n0[3]}},in_n0};
assign w1={{2{in_n1[3]}},in_n1};
assign w2={{2{in_n2[3]}},in_n2};
assign w3={{2{in_n3[3]}},in_n3};
assign sum=w0+w1+w2+w3;
always@*begin
if(sum[5]==1)
out_mean={sum[5],sum[5:2]}+{4\'b0000,(sum[1]|sum[0])};
else
out_mean={sum[5],sum[5:2]};
end
endmodule

 

[Nawroz Qahraman]

On Monday, April 24, 2000 at 3:00:00 AM UTC-4, hsr...@my-deja.com wrote:

Hello,
Could anybody help me as how to use $time in verilog.
I need a timestamp of start of some event and the end of the same.
for instance.
The timestamp should start at the rising edge of a signal called UP and
should end at the rising edge of the other signal DOWN.
The time is actually the diffrence between DOWN - UP.
Please help me.
Hari.

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[Nawroz Qahraman]

The timestamp format is a simple 32-bit counter running at 1MHz, therefore each count is equivalent to 1 microsecond.
The timestamp can be passed into the DUT directly from the testbench as a new 32-bit input.
Please help!!!!!