calculating a config word during operating point analysis

[Svenn Are Bjerkem]

Hi,

I have been trying to get the following problem solved using SpectreHDL
(but also reading in the Verilog-A manual):

How can I generate a config word during the dc operating point analysis
using AHDL or Verilog-A?

I want to simulate a calibration compensation for temperature and
process of an internal resistor which varies quite a lot. The resulting
word is used to switch on and off enough parallell transistors to get
the approximate value. (Running loads of montecarlo runs on different
temperatures)

I have an unclocked successive approximation circuit which manage to
find a 4-bit word during "dc" simulation, (that is during the "ic" run
in a transient simulation). This circuitry is quite heavy and it take
some time to generate that word, but it take even longer time in to find
the word during transient sim.

I have studied the manuals to understand that spectre perform one "ic"
cycle at the beginning to find the initial conditions before going on
doing transient. I have done something like:

module nada (anin anref dout) ()
analog {
if ($analysis("ic")) {
while (compare < reference) {
compare = V(anin);
reference = V(anref);
... convert ii to out[7:0] ...
ii++;
}
}
V(dout[7]) <- $transition(out[7], ... );
....
V(dout[0]) <- $transition(out[0], ... );
}

Beware that there are no variables declared and some lines missing.

My problem is that everything inside the while() loop is not getting out
of the code because I do not reach the V(dout..) lines at the bottom.

A second problem is that the $transition() function seems to stay stuck
at its initial value and not follow the upcount in the while() loop,
even if I move the $transition() statements into the while() loop. (I
can see in the debugger that it steps into the V() assignments without
anything happening on the output pins.

I have the fear that it is not possible to use a high level description
to solve this problem.

Hope for some help,
--
Svenn

 

[fogh]

Svenn Are Bjerkem wrote:

Hi,

I have been trying to get the following problem solved using SpectreHDL
(but also reading in the Verilog-A manual):

How can I generate a config word during the dc operating point analysis
using AHDL or Verilog-A?

I want to simulate a calibration compensation for temperature and
process of an internal resistor which varies quite a lot. The resulting
word is used to switch on and off enough parallell transistors to get
the approximate value. (Running loads of montecarlo runs on different
temperatures)

I have an unclocked successive approximation circuit which manage to
find a 4-bit word during "dc" simulation, (that is during the "ic" run
in a transient simulation). This circuitry is quite heavy and it take
some time to generate that word, but it take even longer time in to find
the word during transient sim.

I have studied the manuals to understand that spectre perform one "ic"
cycle at the beginning to find the initial conditions before going on
doing transient. I have done something like:

module nada (anin anref dout) ()
analog {
if ($analysis("ic")) {
while (compare < reference) {
compare = V(anin);
reference = V(anref);
... convert ii to out[7:0] ...
ii++;
}
}
V(dout[7]) <- $transition(out[7], ... );
...
V(dout[0]) <- $transition(out[0], ... );
}

Beware that there are no variables declared and some lines missing.

My problem is that everything inside the while() loop is not getting out
of the code because I do not reach the V(dout..) lines at the bottom.

A second problem is that the $transition() function seems to stay stuck
at its initial value and not follow the upcount in the while() loop,
even if I move the $transition() statements into the while() loop. (I
can see in the debugger that it steps into the V() assignments without
anything happening on the output pins.

I have the fear that it is not possible to use a high level description
to solve this problem.

Hope for some help,
Hi Svenn,

I can t understand why you have the transitions outside the loop.

 

[Andrew Beckett]

On Thu, 27 Oct 2005 11:29:50 +0200, Svenn Are Bjerkem <svenn.are@bjerkem.de>
wrote:

In article <11lvfbrecakko4a@news.supernews.com>,
cad_support@skipthisandunderscores.catena.nl says...
Hope for some help,
Hi Svenn,
I can t understand why you have the transitions outside the loop.

Simply because of the warning statements in the manual that $transition
should not be executed conditionally, and I have always thought that
while() is a conditional statement.

I hadn't even thought about moving them inside the when() block and I
will try to do so, but I would also like to hear why it would be OK to
ignore the warning

Hi Svenn,

A quick answer here - don't have the time to try out your code to figure out
what is going on.

Anyway, you might want to consider using the "static" analysis instead of "ic",
since this is the DC that preceeds transient etc.

And putting transient inside any conditional is a bad move. It needs to be
evaluated on every iteration, otherwise you loose the history information about
the previous state of a signal, and it will do odd things...

Andrew.

 

[Svenn Are Bjerkem]

In article <86eam1ls4mn58vo92ppo4vv9da8qlt1nv1@4ax.com>,
andrewb@DcEaLdEeTnEcTe.HcIoSm says...

A quick answer here - don't have the time to try out your code to figure out
what is going on.

In the manual it is stated that during DC the output of a $transition()
command is the value of the expression. And I guess that this value is
static.

Anyway, you might want to consider using the "static" analysis instead of "ic",
since this is the DC that preceeds transient etc.

To get my understanding right:
If I disable the dc point calculation in the option form for transient
simulation, then "static" will not be run? (Not that I do, but there are
so many possible DC simulations out there ...)

And putting transient inside any conditional is a bad move. It needs to be
evaluated on every iteration, otherwise you loose the history information about
the previous state of a signal, and it will do odd things...

Yes, this is more than clearly stated in the manual and I try to violate
this only when finding out _why_ it doesn't work.
--
Svenn

 

[Andrew Beckett]

Svenn,

Sorry about the tardiness of my reply - I've been all over the place recently
and have had difficulty giving comp.cad.cadence my normal level of attention.

On Wed, 2 Nov 2005 10:10:34 +0100, Svenn Are Bjerkem <svenn.are@bjerkem.de>
wrote:

In article <86eam1ls4mn58vo92ppo4vv9da8qlt1nv1@4ax.com>,
andrewb@DcEaLdEeTnEcTe.HcIoSm says...
A quick answer here - don't have the time to try out your code to figure out
what is going on.

In the manual it is stated that during DC the output of a $transition()
command is the value of the expression. And I guess that this value is
static.


Anyway, you might want to consider using the "static" analysis instead of "ic",
since this is the DC that preceeds transient etc.

To get my understanding right:
If I disable the dc point calculation in the option form for transient
simulation, then "static" will not be run? (Not that I do, but there are
so many possible DC simulations out there ...)

The "static" is run at the beginning of any analysis. However, it may be if you
do a transient with a readic="filename", and a skipdc=yes, and you don't have
a DC analysis enabled somewhere else, it may not happen - I don't know for
certain.

Unfortunately I don't know for certain - I'd have to try it, and even then I'm
not sure I'd rely upon it!

Regards,

Andrew.

 

[Svenn Are Bjerkem]

In article <11lvfbrecakko4a@news.supernews.com>,
cad_support@skipthisandunderscores.catena.nl says...

Hope for some help,
Hi Svenn,
I can t understand why you have the transitions outside the loop.

Simply because of the warning statements in the manual that $transition
should not be executed conditionally, and I have always thought that
while() is a conditional statement.

I hadn't even thought about moving them inside the when() block and I
will try to do so, but I would also like to hear why it would be OK to
ignore the warning




--
Svenn