S
suresh
Guest
Hello all
I am working on cadence virtouso for some layout. I am using ST 90nm
technology for this. after the layout I dont have Diva files to check
for the DRC so I am using mentors Calibre for the same.
Now for this i am converting the layout into .gui file and following
steps for the DRC ( Calibre) I always get errors no matter how small
my layout may be, I even tried to check for some already exiting ST
90nm files. to my wonder there are errors in this alos. Now I dont
wheter this is correct method to check for the errors using mentor
calibre for a cadence layout.
so can any one suggest me whther the method i am following for DRC is
correct else if there is some other method for design error check,
please let me know. Ur help will greatly appreciated .
thank u very much in advance
Suresh
I am working on cadence virtouso for some layout. I am using ST 90nm
technology for this. after the layout I dont have Diva files to check
for the DRC so I am using mentors Calibre for the same.
Now for this i am converting the layout into .gui file and following
steps for the DRC ( Calibre) I always get errors no matter how small
my layout may be, I even tried to check for some already exiting ST
90nm files. to my wonder there are errors in this alos. Now I dont
wheter this is correct method to check for the errors using mentor
calibre for a cadence layout.
so can any one suggest me whther the method i am following for DRC is
correct else if there is some other method for design error check,
please let me know. Ur help will greatly appreciated .
thank u very much in advance
Suresh