Cadence simulator

[snehashis]

Hii,
Can anybody plz tell how to find total combinational path delay for a
combinational circuit in Cadence verilog simulator?I am using Cadence and
Synopsys design analyzer to find a combinational path delay to estimate
some clock frequency.I can do it by putting a register block at the front
and end of the combinational cloud and then checking maximum operating
frequency ,but that delay will include delays due to flipflops of the regs
as well as wires.So can I find only the delay between the input and output
of a combinational cloud in that simulator?
snehashis

 

[snehashis]

I am using the design analyzer.The problem is -it only gives the maximum
clock frequncy from the critical path calculation.But as i am not using
any registers it is showing no critical path as well as no path to include
the clock duration.what will I do?
snehashis

 

[m]

On Sat, 30 Oct 2004 12:42:05 -0400, "snehashis"
<snehashis_iitkgp@yahoo.co.in> wrote:

I am using the design analyzer.The problem is -it only gives the maximum
clock frequncy from the critical path calculation.But as i am not using
any registers it is showing no critical path as well as no path to include
the clock duration.what will I do?

as i have mentioned, you can use "report_delay -from x -to y" to get
delays which are unconstrained. read the "help report_delay" output
carefully. or check the actual documentation.

 

[m]

On Fri, 29 Oct 2004 13:39:40 -0400, "snehashis"
<snehashis_iitkgp@yahoo.co.in> wrote:

Hii,
Can anybody plz tell how to find total combinational path delay for a
combinational circuit in Cadence verilog simulator?I am using Cadence and
Synopsys design analyzer to find a combinational path delay to estimate
some clock frequency.I can do it by putting a register block at the front
and end of the combinational cloud and then checking maximum operating
frequency ,but that delay will include delays due to flipflops of the regs
as well as wires.So can I find only the delay between the input and output
of a combinational cloud in that simulator?
snehashis

to do delay calculation, the tool you need is a timing analyzer not a
simulator. you can use design_analyzer as a timing analyzer where you
can get a timing report from an input to an output.

 

[Tom Verbeure]

You could do this with DC:

create_clock dummy_clock 1
set_input_delay -clock dummy_clock 0 all_inputs()
set_output_delay -clock dummy_clock 0 all_outputs()
report_timing

I didn't check it, but it should work (after fixing possible syntax
errors.)

Tom