Cadence, shortened net, global pins

[StreAMnewal]

1) When I try to short pins such as vdda! with pin created by me I see
errors.
2) Also When I try to short pins vdda with vdde I see errors. What the
problem?
3) How crete global pins in schematic without making that on symbol? I
need to use pins with same names in ierarchy.

http://
img227.imageshack.us/img227/1338/globalnetshortened.th.png
http://
img227.imageshack.us/img227/511/globalnet2error.th.png

How can I solve that problems?

 

[Andrew Beckett]

StreAMnewal wrote, on 04/14/10 12:31:

1) When I try to short pins such as vdda! with pin created by me I see
errors.
2) Also When I try to short pins vdda with vdde I see errors. What the
problem?
3) How crete global pins in schematic without making that on symbol? I
need to use pins with same names in ierarchy.

http://
img227.imageshack.us/img227/1338/globalnetshortened.th.png
http://
img227.imageshack.us/img227/511/globalnet2error.th.png

How can I solve that problems?

Well, why are you shorting them? You cannot short pins to globals, globals to
globals, or pins to pins (certainly not in IC5141 - CDB just doesn't support
this). Whilst in theory OpenAccess would allow this, it would require a lot of
changes throughout the tools for this to be supported.

The general workaround is to use the "cds_thru" component from the "basic"
library. This is a virtual short - it can be seen as an iprobe for spectre, or a
zero-volt source, or Virtuoso XL can treat it as a short, and Assura can short
the component (provided there's support in your rules), etc, etc.

Regards,

Andrew.

 

[Andrew Beckett]

StreAMnewal wrote, on 04/14/10 19:55:

Thanks, Andrew.

I am a little confused. I have another question.
What the globals? is it vdda or vdde?

How can I create pin that will be used in Schematic scheme and in the
upper ierarchy of Schematic scheme?

I need to short vdda or vdde with pins because i shortened them with a
bulk of pmos4 everywhere in schemes of project,
Different signal to different pmos4.
I need to add signal such as power to vdda thar i short with bulk.

Those tap symbols you've placed on your schematic (vddd, veed, veea etc) have
defined the net connected to them as being global signals (named vddd!, veed!
(note the exclamation mark at the end). This means that any schematic in the
hierarchy which uses the same name will have those nets connected to each other
- because they are global.

The pins (such as as +5Vaa +5Va) are explicit connections through the hierarchy;
you would wire up to the pins on the corresponding symbol, and the connections
would go through the hierarchy.

It is illegal to have a connection which is both an explicit pin, and global, if
the names are different - it's a short.

There are a few cases where you are allowed to "alias" net names - you can use
things like the "patch" component in basic, or you can (for example) label a
wire differently to the pin to which is connected. However, that allows you to
"alias" an internal net - it does not allow you to connect a pin to a pin (which
is a short) or a pin to a global (also a short) or a global to a global (Also a
short).

Fundamentally you have discovered why using global signals is a bad idea!

As I said before, you could use the cds_thru to create a virtual short - it all
depends on what you're doing with the schematic. Sometimes people consciously
have the bulk nets separate, and then connect them using a "metal resistor" on
the layout (often just a marker over a track to make LVS extract it as a small
value resistor - this means you can ensure that each side of this "resistor" is
connected to the expected components, but yet they are joined in reality).

Anyway, your question is a bit confusing - probably because of your English -
but I _think_ I've described what you're trying to solve. Unfortunately if you
don't know what a global signal is, you probably need to do some reading of the
documentation, and I'd worry about whether how you've structured your schematics
makes sense.

Regards,

Andrew.

 

[StreAMnewal]

Thanks, Andrew.

I am a little confused. I have another question.
What the globals? is it vdda or vdde?

How can I create pin that will be used in Schematic scheme and in the
upper ierarchy of Schematic scheme?

I need to short vdda or vdde with pins because i shortened them with a
bulk of pmos4 everywhere in schemes of project,
Different signal to different pmos4.
I need to add signal such as power to vdda thar i short with bulk.

 

[Andrew Beckett]

StreAMnewal wrote, on 04/15/10 15:10:

Thanks, Andrew.
The pins (such as as +5Vaa +5Va) are explicit connections through the hierarchy;
you would wire up to the pins on the corresponding symbol, and the connections
would go through the hierarchy.
How can I wire up the pins in "Schematics"?
As I understood I need to add "!" to the end of pin name so this would
connect with same name pin through hierarchy.
//Sorry for my English

I don't understand your question. So I'm taking a guess at what you're asking.

Normally you would not have ! in the name of pins - because there's not much
point making it a pin if it's global (and adding the ! would make the net global).

Pins in a schematic connections into a block which must be wired up in the
parent schematic.

Wires labelled with a "!" suffix, or with a "tap" symbol (such as vdd, gnd from
the "basic" library) are global - i.e. all places in the design where the same
name is used, are all connected to each other.

Regards,

Andrew.

 

[StreAMnewal]

Thanks, Andrew.

The pins (such as as +5Vaa +5Va) are explicit connections through the hierarchy;
you would wire up to the pins on the corresponding symbol, and the connections
would go through the hierarchy.
How can I wire up the pins in "Schematics"?

As I understood I need to add "!" to the end of pin name so this would
connect with same name pin through hierarchy.
//Sorry for my English