Cadence schematic format

[m.deng]

I wonder if Cadence schematic file from DFII can be translated into any
other design file format, like EDIF or DEF?

 

[S. Badel]

look here:
CIW->File->Export->...
Design Data Translator's Reference
and of course you can translate to netlists by using the appropriate
netlister...


m.deng wrote:

I wonder if Cadence schematic file from DFII can be translated into any
other design file format, like EDIF or DEF?

 

[m.deng]

S. Badel wrote:

look here:
CIW->File->Export->...
Design Data Translator's Reference
and of course you can translate to netlists by using the appropriate
netlister...


m.deng wrote:

I wonder if Cadence schematic file from DFII can be translated into
any other design file format, like EDIF or DEF?

The CIW exporter can be used to export layout. But what if I want to
export the schematic to be placed and routed?

 

[S. Badel]

with the CIW export you can :
- export schematics to EDIF
- export schematics to CDL
- export to a DEF file as long as you have abstracts for your std cells (if not create by
importing the LEF into cadence) by using Export-PRFlatten to generate autoLayout and then
Export->DEF from the autoLayout.

You can create a verilog netlist using NC-Verilog or VerilogXL integration into Composer. (ie
Tools->Simulation->...)

stéphane

m.deng wrote:

S. Badel wrote:

look here:
CIW->File->Export->...
Design Data Translator's Reference
and of course you can translate to netlists by using the appropriate
netlister...


m.deng wrote:

I wonder if Cadence schematic file from DFII can be translated into
any other design file format, like EDIF or DEF?


The CIW exporter can be used to export layout. But what if I want to
export the schematic to be placed and routed?