Cadence RF Spectre --Bus Error

A

ankjain

Guest
Hi all,
I am getting some "Bus error" while simulating my RF circuit.
Basically I am doing PSS analysis followed by PAC(some sideband error is
also there with PAC, "Sidebands limit reached"). The exact format of the
error is given below:

Error found by spectre during PAC analysis 'sweeppss-004_pac', during
sweep analysis 'sweeppss'

Too many Sidebands requested. You requested 301, the limit is 250

Analysis 'sweeppss-004_pac' terminated prematurely due to error

modelParameter: writing model parameter values to rawfile.
element: writing instance paramenter values to rawfile.

Internal error found in spectre during info 'element'. Please run
'getSpectreFiles' or send the netlist, the spectre log file, the
behavioral model files, and any other information that can help identify
the problem to support@cadence.com

Bus Error
 
On Wed, 08 Jun 2005 09:08:39 -0400, ankjain wrote:

Hi all,
I am getting some "Bus error" while simulating my RF circuit.
Basically I am doing PSS analysis followed by PAC(some sideband error is
also there with PAC, "Sidebands limit reached"). The exact format of the
error is given below:

Error found by spectre during PAC analysis 'sweeppss-004_pac', during
sweep analysis 'sweeppss'

Too many Sidebands requested. You requested 301, the limit is 250

Analysis 'sweeppss-004_pac' terminated prematurely due to error

modelParameter: writing model parameter values to rawfile.
element: writing instance paramenter values to rawfile.

Internal error found in spectre during info 'element'. Please run
'getSpectreFiles' or send the netlist, the spectre log file, the
behavioral model files, and any other information that can help identify
the problem to support@cadence.com

Bus Error
Click to expand...
A bus error is a type of memory access error similar to a seg fault, so
Cadence is crashing. Looks like your simulation setup is somehow wrong,
and the simulator tries to exit. The exit is not clean and a bus
error signal is generated, Cadence catches the signal to give you an
internal error message, and then crashes. The bus error is a Cadence
bug, but if you fix the sideband error (sorry, I can't help you with
that), it should be fine.

Frank
 
Frank, thanks for the enlightenment. Have successfully fixed the sideband
error, but now the error message is "Insufficient Memory Available".
PSS/PAC analysis usually generates run time temporary swap files which
easily eat up to GBs of space. I checked Harddisk capacity also which was
sufficient at the time it was giving this error. And I cant change the
capacity of RAM as its server related thing (Anyway there's enough of swap
memory available). So what else can be done? Any idea ?

Ankur
 
On Fri, 10 Jun 2005 07:58:35 -0400, ankjain wrote:

Frank, thanks for the enlightenment. Have successfully fixed the sideband
error, but now the error message is "Insufficient Memory Available".
PSS/PAC analysis usually generates run time temporary swap files which
easily eat up to GBs of space. I checked Harddisk capacity also which was
sufficient at the time it was giving this error. And I cant change the
capacity of RAM as its server related thing (Anyway there's enough of swap
memory available). So what else can be done? Any idea ?

Ankur
Click to expand...
The swap file in general is of limited size (perhaps a separate partition)
and will not grow to fill the entire hard drive (though this depends on
the OS). I'm not sure what triggers the memory error - maybe you're
exceeding the max size of addressable memory (2-4GB on a 32-bit system).
What OS do you have and how much memory? If you don't have any machines
with more memory then your design might just be too large to simulate
with your current simulation parameters. Maybe you should try to determine
if there are any simulation parameters that will reduce the required
memory, change the timesteps or simulation runtime, or split the design
into smaller blocks. I don't really know since I haven't used that
simulator.

Frank
 
I do not know if this will help me, but it might be worth trying:

I did get some problems with memory usage before with this error message

*Error* cdsSpice process has expired

I solved this problem with this:

; increase the number to increase the memory allocated to HSpice
; for exporting large netlists
cdsSpice.init languageSize int 10000
cdsSpice.init spiceSize int 10000
hspiceS.init languageSize int 10000
hspiceS.init spiceSize int 10000



On 2005-06-10 20:33:58 -0400, "Frank E. Gennari"
<gennari_REMOVE_THIS_@eecs.berkeley.edu> said:

On Fri, 10 Jun 2005 07:58:35 -0400, ankjain wrote:
Frank, thanks for the enlightenment. Have successfully fixed the sideband
error, but now the error message is "Insufficient Memory Available".
PSS/PAC analysis usually generates run time temporary swap files which
easily eat up to GBs of space. I checked Harddisk capacity also which was
sufficient at the time it was giving this error. And I cant change the
capacity of RAM as its server related thing (Anyway there's enough of swap
memory available). So what else can be done? Any idea ?
Ankur

The swap file in general is of limited size (perhaps a separate partition)
and will not grow to fill the entire hard drive (though this depends on
the OS). I'm not sure what triggers the memory error - maybe you're
exceeding the max size of addressable memory (2-4GB on a 32-bit system).
What OS do you have and how much memory? If you don't have any machines
with more memory then your design might just be too large to simulate
with your current simulation parameters. Maybe you should try to determine
if there are any simulation parameters that will reduce the required
memory, change the timesteps or simulation runtime, or split the design
into smaller blocks. I don't really know since I haven't used that
simulator.

Frank


--
Click to expand...
Stefan Robert
(to email: remove the numbers)
 
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