cadence mixed signal, init registers?

[raf]

Hi,

I have two issues with my mixed signal simulations:

1) I am running spectreSVerilog simulations to debug some of the verilog
code we have to control our analog chip. It seems that in order for
anything to work I need to initialize all registers first. I just want
all registers to initialize to 0 by default, is there any way to do this
without explicitly writing an init statement for each register? I'd
rather not modify the verilog code at all.

2) When I view the waveforms they are all superimposed on eachother. Now
usually I just use the "To Split" "To Composite" option, however this
has no effect. What could be wrong?

Thanks for your help,
-Raf