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D
Djamel DELLAA
Guest
Le jeudi 20 juillet 1995 à 08:00:00 UTC+1, VLSI a écrit :
Hello,
Send me your ES2 CDK (PDK) and I\'ll test it on our Cadence
Please could anyone translate this error message I get when trying to simulate
a schematic on design framework II for the ES2 1 micron process. The design
composes of a series of blocks for a ROM, ie the input latch, row decoder and
PLA for output signals followed by output latch. The error message is in the
si.log file and is as follows :
------------------------------------------------------------------------------
si: Loading simulation environment file \"/homedir/mkh/GLiTCH/rom.run2/si.env\".
si: Loading user defined simulation run control file \"/opt/ecad/kits/es2_cdk_v300/.simrc\".
Running ES2prepHspice
Running ES2prepHspice
si: Loading simulation capabilities file \"/opt/ecad/9401/tools.sun4/dfII/etc/skill/si/simcap.ile\".
si: The default value of the variable \"simControlFile\" has been overridden.
si: The default value of the variable \"simTimeUnit\" has been overridden.
si: The default value of the variable \"simReNetlistAll\" has been overridden.
si: The default value of the variable \"simDoPostLayout\" has been overridden.
si: The default value of the variable \"hspiceSimViewList\" has been overridden.
si: The default value of the variable \"hspiceSimStopList\" has been overridden.
Running simulation in directory: \"/homedir/mkh/GLiTCH/rom.run2\".
Running ES2prepModel
Running netlist
Begin netlist: Jul 20 14:57:43 1995
simulation library path = \"/homedir/mkh/GLiTCH /ecad/kits/es2_cdk_v300/ecpd10 /ecad/kits/es2_cdk_v300/common \"
simulation library = ROM
cell = Romtest
view = schematic
version name = current
view list = (\"hspice\" \"spice\" \"extracted\" \"cmos.sch\" \"schematic\" \"symbol\")
stopping view list = (\"hspice\" \"spice\" \"symbol\")
End netlist: Jul 20 14:59:27 1995
Running simin
Running ES2prepareSpiceNetlist
*Error* arrayref: array index out of bounds - map[2447]
---------------------------------------------------------------------------------
Thank you in advance.
Yours sincerely,
M.N.K.
Hello,
Send me your ES2 CDK (PDK) and I\'ll test it on our Cadence
D
Djamel DELLAA
Guest
Le jeudi 20 juillet 1995 à 08:00:00 UTC+1, VLSI a écrit :
Hello,
Send me your ES2 CDK (PDK) and I\'ll test it on our Cadence
Please could anyone translate this error message I get when trying to simulate
a schematic on design framework II for the ES2 1 micron process. The design
composes of a series of blocks for a ROM, ie the input latch, row decoder and
PLA for output signals followed by output latch. The error message is in the
si.log file and is as follows :
------------------------------------------------------------------------------
si: Loading simulation environment file \"/homedir/mkh/GLiTCH/rom.run2/si.env\".
si: Loading user defined simulation run control file \"/opt/ecad/kits/es2_cdk_v300/.simrc\".
Running ES2prepHspice
Running ES2prepHspice
si: Loading simulation capabilities file \"/opt/ecad/9401/tools.sun4/dfII/etc/skill/si/simcap.ile\".
si: The default value of the variable \"simControlFile\" has been overridden.
si: The default value of the variable \"simTimeUnit\" has been overridden.
si: The default value of the variable \"simReNetlistAll\" has been overridden.
si: The default value of the variable \"simDoPostLayout\" has been overridden.
si: The default value of the variable \"hspiceSimViewList\" has been overridden.
si: The default value of the variable \"hspiceSimStopList\" has been overridden.
Running simulation in directory: \"/homedir/mkh/GLiTCH/rom.run2\".
Running ES2prepModel
Running netlist
Begin netlist: Jul 20 14:57:43 1995
simulation library path = \"/homedir/mkh/GLiTCH /ecad/kits/es2_cdk_v300/ecpd10 /ecad/kits/es2_cdk_v300/common \"
simulation library = ROM
cell = Romtest
view = schematic
version name = current
view list = (\"hspice\" \"spice\" \"extracted\" \"cmos.sch\" \"schematic\" \"symbol\")
stopping view list = (\"hspice\" \"spice\" \"symbol\")
End netlist: Jul 20 14:59:27 1995
Running simin
Running ES2prepareSpiceNetlist
*Error* arrayref: array index out of bounds - map[2447]
---------------------------------------------------------------------------------
Thank you in advance.
Yours sincerely,
M.N.K.
Hello,
Send me your ES2 CDK (PDK) and I\'ll test it on our Cadence
V
Vishesh Gupta
Guest
On Thursday, June 7, 2012 at 11:31:07 AM UTC+5:30, Sam wrote:
Thanks, buddy...I was having the same problem and it worked!On Thursday, 7 June 2012 00:29:30 UTC+5:30, Jean-Marc Bourguet wrote:
Sam <samir...@gmail.com> writes:
Dear all,
I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB
version). I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS
5.8. I am using UMC 180nm technology node. It seems I have properly set
the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just
thought to verify that all the licensed features are working fine or not.
So, using Schematic XL I have created a simple inverter and did a
transient analysis using ADE (G)XL. It worked fine. Then I tried to open
the layout view using Layout XL. But I got the following error message:
\"(LX-2063): The technology library \'cdsDefTechLib\' contains no constraint
groups that have a \'validLayers\' or \'validVias\' constraint defined. Thus
the XL connectivity extractor is disabled. To enable it, add a
\'validLayers\' constraint to the appropriate constraint group, and ensure
that this constraint group is specified by the \'setupConstraintGroup\'
environment variable.\"
Using the technology library cdsDefTechLib is very suspicious for a layout
and looks like a set up problem. You probably are trying to create the
layout in a library which doesn\'t refer to the tech file of UMC 180 nm.
When you create a library, you are proposed 3 or 4 ways to associate it
with a technology library, you should probably make it reference the one in
your PDK.
Yours,
--
Jean-Marc
Thank you, Jean. After seeing your post I realized that after creating the library with the UMC 1800 nm technology files with alias \'UMC180_Analog\', I renamed the alias to UMC_18_CMOS. And that was causing the problem. Now everything is working fine.
Thank you once again.
V
Vishesh Gupta
Guest
On Thursday, June 7, 2012 at 11:31:07 AM UTC+5:30, Sam wrote:
Thanks, buddy...I was having the same problem and it worked!On Thursday, 7 June 2012 00:29:30 UTC+5:30, Jean-Marc Bourguet wrote:
Sam <samir...@gmail.com> writes:
Dear all,
I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB
version). I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS
5.8. I am using UMC 180nm technology node. It seems I have properly set
the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just
thought to verify that all the licensed features are working fine or not.
So, using Schematic XL I have created a simple inverter and did a
transient analysis using ADE (G)XL. It worked fine. Then I tried to open
the layout view using Layout XL. But I got the following error message:
\"(LX-2063): The technology library \'cdsDefTechLib\' contains no constraint
groups that have a \'validLayers\' or \'validVias\' constraint defined. Thus
the XL connectivity extractor is disabled. To enable it, add a
\'validLayers\' constraint to the appropriate constraint group, and ensure
that this constraint group is specified by the \'setupConstraintGroup\'
environment variable.\"
Using the technology library cdsDefTechLib is very suspicious for a layout
and looks like a set up problem. You probably are trying to create the
layout in a library which doesn\'t refer to the tech file of UMC 180 nm.
When you create a library, you are proposed 3 or 4 ways to associate it
with a technology library, you should probably make it reference the one in
your PDK.
Yours,
--
Jean-Marc
Thank you, Jean. After seeing your post I realized that after creating the library with the UMC 1800 nm technology files with alias \'UMC180_Analog\', I renamed the alias to UMC_18_CMOS. And that was causing the problem. Now everything is working fine.
Thank you once again.