Cadence compiler basics

[PC]

Hi all,

I have a very very basic problem with the cadence VHDL compiler
For example

signal test : std_logic_vector( 15 downto 0);
begin

test<="1111111111111111" ; works fine
test<=x"ffff"; gives an error expecting an expression of type
STD_LOGIC_VECTOR 87[8.3] 93[8.4] why ?

thanks in advance
PC