cadence AMS flow: spectre-ultrasim issues

dinac · Aug 28, 2009

Hi all,

I new to AMS simulation.
Using:-- ic613, mmsim 7.1
simulation using config view.

The digital simulation works well with rtl or with synthesized
netlist.
When simulating for analog using config view, I get errors with
spectre or when using ultra sim
I could have missed some switches.

Is primitve table files for the tech lib really necessary? Could it be
becasue of this?

----------------------spectre
log:--------------------------------------------

Error found by spectre during hierarchy flattening.
Only one instance of a truncate statement is allowed in a
statistics
block.

spectre terminated prematurely due to fatal error.
ncsim: *E,RNALER: Simulation terminated due to analog error.
Memory Usage - 17.9M program + 348.6M data = 366.5M total
CPU Usage - 0.4s system + 0.2s user = 0.6s total (80.4% cpu)
ncsim> exit
------------------------------------------------------------------------------------

--------------ultrasim log -----------------------------------
Error found by UltraSim.
ERROR (USIMDB-12206): The UltraSim simulator could not operate on
the
string values: parameter '5.2E-16*(Nx*0.25)*((El+0.04)*1.923)
**0.7' in
instance 'Q5', in subcircuit
'Tutorial_SG13_WW+osci_60G_tut+schematic_LVS+0x10000001'
called by
'MixSPIVCO.I1'.

UltraSim failed.
ncsim: *E,RNALER: Simulation terminated due to analog error.
Memory Usage - 17.9M program + 394.8M data = 412.6M total
CPU Usage - 0.1s system + 0.4s user = 0.6s total (17.5% cpu)
ncsim> exit
-----------------------------------------------------------------

Thanks a lot

cheers
dinac.

Riad KACED · Aug 30, 2009

Hi Dinac,

I'm trying to comment the Spectre bit ...
It appears like you have more than one 'truncate' statement in some
Statitistic statement. The truncate is used to alter the default 4
Sigma in Gauss distribs. Would you mind to check this ? Juste serach
the truncate keyword in your model card although the Spectre tells you
the line number.

BTW, Are you having the same behaviour when running direct Spectre/
Ultrasim. I mean out the AMS environment.
Just run your Design using Spectre and see what's happenning ...

Regards,
Riad.

dinac · Aug 30, 2009

Hi Riad, all

Thanks Riad for your reply. it helped me a lot.
I did a trial simulation by commenting out the 'truncate statement'
and it works.
I do not know, what can be done with the truncate statement, I guess
it is needed to do a monte-carlo or statistical simulation.
I may have to figure out a work-around to do this.

i am using the same configuration for the Ultrasim, I just change the
solver to 'Ultrasim' and carry out the same simulation.
The Ultrasim stops with the same errors as the previous log, which i
have attached.

Thanks

cheers,
dinac

Riad KACED · Aug 30, 2009

Hi Dinac,

This is a bit of information about the truncate factor from the
Virtuoso Spectre Circuit Simulator User Guide:
------------------------
Truncation Factor: The default truncation factor for Gaussian
distributions (and for the Gaussian distribution underlying the log
normal distribution) is 4.0 sigma. Randomly generated values that are
outside the range of mean + 4.0 sigma are automatically rejected and
regenerated until they fall inside the range. You can change the
truncation factor using the truncate statement. The following is the
syntax: truncate tr=value
Note: The value of the truncation factor can be a constant or an
expression.
Note: Parameter correlations can be affected by using small truncation
factors.
------------------------

You can for example write a statistics block as following:
statistics {
process {
vary u0 dist=gauss std=1/3
vary vth0 dist=gauss std=1/3
truncate tr=6.0
}
mismatch {
vary u0 dist=gauss std=1
vary vth0 dist=gauss std=1
truncate tr=6.0
}
}

Running either direct Spectre or AMS with Spectre Solver must be fine
with a model file containing the above. But if you duplicate the
truncate statement in either process, mismatch blocks or the
statistics bloc itself, then Spectre won't be happy with it.
Personally, I don't see any reason for Spectre to complain although it
does not make any sense to duplicate the truncate statement within a
given block.

So if I miss about the above statistics bloc and write the following
instead:

statistics {
truncate tr=6.0
truncate tr=5.0
process {
vary hv_u0_ne dist=gauss std=1/3
vary hv_vth0_ne dist=gauss std=1/3
truncate tr=6.0
truncate tr=6.0
}
mismatch {
vary hv_u0_ne dist=gauss std=1
vary hv_vth0_ne dist=gauss std=1
truncate tr=6.0
truncate tr=6.0
}
}

Then Spectre would report the following errors:

Error found by spectre during hierarchy flattening.
"/home/rk/rkSpectreModels/rk_mos.scs"
29: All truncate statements in the netlist must have the same
value for
'tr'. Another truncate statement
(`/home/rk/rkSpectreModels/rk_mos.scs',
line 28) was found with different 'tr' value.
Only one instance of a truncate statement is allowed in a process
block.
Only one instance of a truncate statement is allowed in a mismatch
block.

The above errors arise with both Spectre direct (spectre -W =
7.1.1.169.isr10) and AMS/spectre (print_mmsimver = 7.1.1.140.isr8)
from IUS 08.20-s014.
Would you mind to post you versions ?

In summary, having one 'truncate' statement in a statistics block
should be fine. That's the duplication that makes Spectre aborting.
Otherwise, you might share your case with your CDS AE providing your
tetscase along with your IUS version.

Again, I leave the Ultrasim bit for Andrew or any other fellows ...

Cheers,
Riad.

Andrew Beckett · Sep 1, 2009

Riad KACED wrote, on 08/30/09 17:06:
.... snipped ...

The above errors arise with both Spectre direct (spectre -W =
7.1.1.169.isr10) and AMS/spectre (print_mmsimver = 7.1.1.140.isr8)
from IUS 08.20-s014.
Would you mind to post you versions ?

In summary, having one 'truncate' statement in a statistics block
should be fine. That's the duplication that makes Spectre aborting.
Otherwise, you might share your case with your CDS AE providing your
tetscase along with your IUS version.

Again, I leave the Ultrasim bit for Andrew or any other fellows ...

Cheers,
Riad.

For the Ultrasim bit, perhaps you could post the bit of the netlist that it is
complaining about?

Regards,

Andrew.

dinac · Sep 2, 2009

Hi Riad, Andrew,

Thanks a lot Riad for your detailed answer.
Actually, when i did a search for a 'truncate' statement, I found each
of the truncate statement
in 2 model file (each for resistor, mos devices), which are included
in the model tech
The truncate statements are not duplicated, each of these model file
as only one defined for each.

Andrew, Thanks for your reply. I will try to attach a netlist soon.

Thanks again for your replies.

cheers
dinac

dinac · Oct 5, 2009

Hi Andrew and other AMS experts,

I am still facing the same problem.
i had actually overcome this issue by using IUS8,1 and MMSIM70 and the
simulation was running perfectly. But I have licenses for limited
period and so had to switch back.

And now back with the similar issue, using: IUS611usr3 and MMSIM701

Thanks

cheers
Dinac

Here is the log file:
-----------------------------------------------------------------------------------------------------------------
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/Digidesign/buffcell/schematic/
verilog.vams
module Digidesign.buffcell:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Digidesign' 'buffcell' 'schematic').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/DigiDesign/SPIslave_vco/schematic/
verilog.vams
module Digidesign.SPIslave_vco:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Digidesign' 'SPIslave_vco' 'schematic').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/Digidesign/Tutorial_design/switch/
schematic/verilog.vams
module Tutorial_design.switch:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Tutorial_design' 'switch' 'schematic').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/Tutorial_design/osci_design/
schematic_sim/verilog.vams
module Tutorial_design.osci_design:schematic_sim (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Tutorial_design' 'osci_design'
'schematic_sim').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/mixspi_design/top_design/schematic/
verilog.vams
module mixspi_design.top_design:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('mixspi_design' 'top_design' 'schematic').
Compilation successful.
ncelab: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
ncelab: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncelab 06.11-s002
HOSTNAME: sun55
OPERATING SYSTEM: Linux 2.6.9-67.0.15.ELsmp #1 SMP Tue Apr 22
13:58:43 EDT 2008 x86_64
MESSAGE: sv_seghandler - trapno -1
-----------------------------------------------------------------
Failed to elaborate ("mixspi_design" "top_design" "config_design").

Andrew Beckett · Oct 5, 2009

dinac wrote, on 10/05/09 10:10:

Hi Andrew and other AMS experts,

I am still facing the same problem.
i had actually overcome this issue by using IUS8,1 and MMSIM70 and the
simulation was running perfectly. But I have licenses for limited
period and so had to switch back.

And now back with the similar issue, using: IUS611usr3 and MMSIM701

Thanks

cheers
Dinac

Here is the log file:
-----------------------------------------------------------------------------------------------------------------
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/Digidesign/buffcell/schematic/
verilog.vams
module Digidesign.buffcell:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Digidesign' 'buffcell' 'schematic').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/DigiDesign/SPIslave_vco/schematic/
verilog.vams
module Digidesign.SPIslave_vco:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Digidesign' 'SPIslave_vco' 'schematic').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/Digidesign/Tutorial_design/switch/
schematic/verilog.vams
module Tutorial_design.switch:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Tutorial_design' 'switch' 'schematic').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/Tutorial_design/osci_design/
schematic_sim/verilog.vams
module Tutorial_design.osci_design:schematic_sim (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('Tutorial_design' 'osci_design'
'schematic_sim').
ncvlog: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
file: /home/cadence/ProjectDir/cdb/mixspi_design/top_design/schematic/
verilog.vams
module mixspi_design.top_design:schematic (up-to-date)
errors: 0, warnings: 0
Successfully compiled ('mixspi_design' 'top_design' 'schematic').
Compilation successful.
ncelab: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.
Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
ncelab: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncelab 06.11-s002
HOSTNAME: sun55
OPERATING SYSTEM: Linux 2.6.9-67.0.15.ELsmp #1 SMP Tue Apr 22
13:58:43 EDT 2008 x86_64
MESSAGE: sv_seghandler - trapno -1
-----------------------------------------------------------------
Failed to elaborate ("mixspi_design" "top_design" "config_design").

Did you do what it suggested to do, and contact Cadence?

BTW, why can't you get newer licenses? That shouldn't be a problem for any
customer on maintenance...

Regards,

Andrew.

Riad KACED · Oct 5, 2009

Hi Dinac,

Moving to latest IUS82/MMSIM71 versions is pretty much with no impact
at all on your design flow.
Given the new features in IUS82, I would rather advise convincing your
manager/team to move forward.
As per the licenses cost, I'm not really fit enough to make an
objective comment.

Cheers,
Riad.

dinac · Oct 6, 2009

Thanks a lot for your replies, Andrew and Riad.
Actually we are using licenses provided by Europractise. So I do not
know how things has to go.

I will contact the cadence in this regard.

cheers
Dinac

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