A
ANeyer
Guest
Hello,
I've just synthesized a small HDL design using Cadence/Ambit BuildGates
(by running >do_build_generic).
My question, is it possible to do post-synthesis simulation on the
synthesized design. I've exported the design to a verilog-netlist
(write_verilog -hierarchical $db_dir/filename.v), but I cannot find any
Ambit/Buildgates simulation models (e. g. for Modelsim or NCSim).
Of course I can do the technology mapping (>do_optimize), export the
netlist and do a simulation on the final technology depending design.
But I'd like to take an intermediate step by simulating the unmapped design.
Thanks,
Andreas
I've just synthesized a small HDL design using Cadence/Ambit BuildGates
(by running >do_build_generic).
My question, is it possible to do post-synthesis simulation on the
synthesized design. I've exported the design to a verilog-netlist
(write_verilog -hierarchical $db_dir/filename.v), but I cannot find any
Ambit/Buildgates simulation models (e. g. for Modelsim or NCSim).
Of course I can do the technology mapping (>do_optimize), export the
netlist and do a simulation on the final technology depending design.
But I'd like to take an intermediate step by simulating the unmapped design.
Thanks,
Andreas