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TalentLab is a high tech search firm headquartered in Ottawa, Canada
and we have clients throughout North America. To learn more please
visit http://www.talentlab.com
DFT Manager
The Role
The DFT manager position provides direction and expertise for the
evaluation, development, and implementation of DFT solutions for
current and future designs. Your team's charter is to improve
testability, reduce test escapes, improve debug capabilities, speed
time to market, and reduce test cost.
Responsibilities:
1. Gain a clear understanding of the design and defect density of the
technology to formulate the test/debug requirements and strategies for
the design.
2. You will work closely with EDA and ATE vendors to understand and
influence their product roadmaps in order to deliver DFT technologies,
which can scale with the increasing design complexity.
3. Provide turnkey solutions to test/debug requirements by establishing
DFT flow methodology that is easily integrated into the existing design
flow. Specifically, your team will own flows for: DFT architecture,
testability analysis, DFT logic implementation and verification, test
synthesis, timing verification/closure, ATPG, fault coverage/grading,
failure analysis and fault isolation.
4. Provide solutions for at-speed testing as well as speed grading for
current and future designs. In the current test paradigm, this includes
manual test generation (functional patterns) as well as structured DFT
techniques (transition and path delay ATPG).
5. Support product/test team in pattern validation, design
characterization efforts. Assist with prototype debug and provide
production support to identify yield improvements.
Qualifications:
ˇ Must have extensive hands-on experience in logic design flow:
micro-architecture, modeling, RTL implementation/verification, logic
synthesis, logic equivalent checking, static timing analysis, signal
integrity checks, and back-end support for timing closure.
ˇ Must have a firm understanding and hands-on experience on industry
standard DFT techniques: boundary scan (AC/DC), memory BIST and repair,
logic BIST/pattern compression, analog BIST, BIST for high-speed serial
links, etc.
ˇ Must be knowledgeable on design and manufacturing issues impacting
DPM and methods to overcome them. Must also have a clear understanding
of the test/product engineering process in order to support their
efforts.
ˇ Ready to take on a key management role, managing multi projects
simultaneously. Must be able to leverage/engage subcontractors and
vendors to assure timely delivery of milestones. Must have enough
breadth to manage, motivate, and retain a diverse talent pool.
Cheers,
Stuart Musson
Talent Agent
(613) 791-7890 Direct
(613) 592-6666 Fax
stuart@talentlab.com
http://www.talentlab.com
and we have clients throughout North America. To learn more please
visit http://www.talentlab.com
DFT Manager
The Role
The DFT manager position provides direction and expertise for the
evaluation, development, and implementation of DFT solutions for
current and future designs. Your team's charter is to improve
testability, reduce test escapes, improve debug capabilities, speed
time to market, and reduce test cost.
Responsibilities:
1. Gain a clear understanding of the design and defect density of the
technology to formulate the test/debug requirements and strategies for
the design.
2. You will work closely with EDA and ATE vendors to understand and
influence their product roadmaps in order to deliver DFT technologies,
which can scale with the increasing design complexity.
3. Provide turnkey solutions to test/debug requirements by establishing
DFT flow methodology that is easily integrated into the existing design
flow. Specifically, your team will own flows for: DFT architecture,
testability analysis, DFT logic implementation and verification, test
synthesis, timing verification/closure, ATPG, fault coverage/grading,
failure analysis and fault isolation.
4. Provide solutions for at-speed testing as well as speed grading for
current and future designs. In the current test paradigm, this includes
manual test generation (functional patterns) as well as structured DFT
techniques (transition and path delay ATPG).
5. Support product/test team in pattern validation, design
characterization efforts. Assist with prototype debug and provide
production support to identify yield improvements.
Qualifications:
ˇ Must have extensive hands-on experience in logic design flow:
micro-architecture, modeling, RTL implementation/verification, logic
synthesis, logic equivalent checking, static timing analysis, signal
integrity checks, and back-end support for timing closure.
ˇ Must have a firm understanding and hands-on experience on industry
standard DFT techniques: boundary scan (AC/DC), memory BIST and repair,
logic BIST/pattern compression, analog BIST, BIST for high-speed serial
links, etc.
ˇ Must be knowledgeable on design and manufacturing issues impacting
DPM and methods to overcome them. Must also have a clear understanding
of the test/product engineering process in order to support their
efforts.
ˇ Ready to take on a key management role, managing multi projects
simultaneously. Must be able to leverage/engage subcontractors and
vendors to assure timely delivery of milestones. Must have enough
breadth to manage, motivate, and retain a diverse talent pool.
Cheers,
Stuart Musson
Talent Agent
(613) 791-7890 Direct
(613) 592-6666 Fax
stuart@talentlab.com
http://www.talentlab.com