C to Verilog

[Nadav Rotem]

Hello,

My name is Nadav and I am the author of http://www.C-to-Verilog.com ;
This website allows FPGA developers to take regular C code and
"compile" it into Verilog. The Verilog code can be verified with the
auto generated test-bench and then synthesized to an FPGA. There is a
video that shows how it is done. The compiler tries to "pipeline" as
much code as possible to get a design which is fast, operates at high
clock frequencies and takes few resources.

I would appreciate any feedback regarding the output designs, feature
requests, etc.

Nadav Rotem

 

[Jason Zheng]

On Sat, 13 Dec 2008 03:22:50 -0800 (PST)
Nadav Rotem <nadav256@gmail.com> wrote:

Hello,

My name is Nadav and I am the author of http://www.C-to-Verilog.com ;
This website allows FPGA developers to take regular C code and
"compile" it into Verilog. The Verilog code can be verified with the
auto generated test-bench and then synthesized to an FPGA. There is a
video that shows how it is done. The compiler tries to "pipeline" as
much code as possible to get a design which is fast, operates at high
clock frequencies and takes few resources.

I would appreciate any feedback regarding the output designs, feature
requests, etc.

Nadav Rotem

Nadav,

Do you have any whitepaper describing how the conversion is done in
concept (I'm not talking about the user interface)? I took a quick look
at the online example, and the result output.v file is very difficult
to read as the variable names have no suggestion what exactly they do.

How does your tool compare to other HLS tools based on C, such as
Synfora and Y Exploration?

--
Comedy, like Medicine, was never meant to be practiced by the general
public.

 

[glen herrmannsfeldt]

Nadav Rotem <nadav256@gmail.com> wrote:

My name is Nadav and I am the author of http://www.C-to-Verilog.com ;
This website allows FPGA developers to take regular C code and
"compile" it into Verilog.

I have not found such systems very interesting, but that
might be because of what I expect from verilog.

I would find it useful if I could take an algorithm in C
and convert it to verilog. For the problems I work on, the
verilog implementation is so different from the C implementation
that there is pretty much no chance software (not to mention
most programmers) would figure out the conversion.

A matrix operation in C might be done with nested for loops.
In verilog it might be a systolic array carefully arranged
such that the appropriate operations can be done in parallel.

The C code likely has to initialize some variables before
the loops. Things that are done only once should be done
by external code driving the FPGA. (Or maybe in a processor
on/in the FPGA.) The thought process for writing good verilog
code for a pipelined hardware implementation of an algorithm
and for writing fast C code are so different that it is
pretty much impossible to expect automated conversion.

-- glen

 

[Ramesh]

On Dec 17, 2:28 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Nadav Rotem <nadav...@gmail.com> wrote:
My name is Nadav and I am the author ofhttp://www.C-to-Verilog.com;
This website allows FPGA developers to take regular C code and
"compile" it into Verilog.

I have not found such systems very interesting, but that
might be because of what I expect from verilog.

I would find it useful if I could take an algorithm in C
and convert it to verilog.  For the problems I work on, the
verilog implementation is so different from the C implementation
that there is pretty much no chance software (not to mention
most programmers) would figure out the conversion.

A matrix operation in C might be done with nested for loops.
In verilog it might be a systolic array carefully arranged
such that the appropriate operations can be done in parallel.

The C code likely has to initialize some variables before
the loops.  Things that are done only once should be done
by external code driving the FPGA.  (Or maybe in a processor
on/in the FPGA.)   The thought process for writing good verilog
code for a pipelined hardware implementation of an algorithm
and for writing fast C code are so different that it is
pretty much impossible to expect automated conversion.  

-- glen

"Pretty much impossible" is perhaps an overstatement.

There is quite a bit of compiler work on vectorization, pipelining,
simd code generation of math/matrix code. All of these techniques
apply to generating vectorized / pipelined and/or systolic hardware.
A lot of such parallelizing compilers tend to allow some hints/meta-
comments etc. to let the user direct the compiler.
There is not much commercial work in the area of high level synthesis
for math/matrix oriented code; it might be a function of market demand
as well as problem complexity.

Some approaches take a library based approach where matrix operations
are expressed at a high level.
Matlab which represents matrix operations explicitly has options to
target various parallel hardware as well as generate synthesizable
verilog RTL from Matlab descriptions.

 

[glen herrmannsfeldt]

Ramesh <ditsdad@gmail.com> wrote:
(snip on C to verilog discussion)

"Pretty much impossible" is perhaps an overstatement.

There is quite a bit of compiler work on vectorization, pipelining,
simd code generation of math/matrix code. All of these techniques
apply to generating vectorized / pipelined and/or systolic hardware.
A lot of such parallelizing compilers tend to allow some hints/meta-
comments etc. to let the user direct the compiler.
There is not much commercial work in the area of high level synthesis
for math/matrix oriented code; it might be a function of market demand
as well as problem complexity.

Some approaches take a library based approach where matrix operations
are expressed at a high level.
Matlab which represents matrix operations explicitly has options to
target various parallel hardware as well as generate synthesizable
verilog RTL from Matlab descriptions.

Even so, Matlab is serial and verilog, implemented in hardware,
tends to be parallel. Also, a systolic array tends to
vary in size with the size of the problem, which complicates
hardware implmementations. I have worked on ones with virtual
pipelines allowing larger problems than the size of the array,
and longer run times. For some matrix operations, I might
believe one could generate a systolic array from matlab code.

-- glen