C-Systemc-VHDL problem in Modelsim

M

Mr. Peterfolk

Guest
Hi,

I have the following problem:
I want to verify my RTL code (written in VHDL) with the golden
reference (written in C). The connection between the two model is the
SystemC (Wrapper), the simulator is the Modelsim.
I want to observe a HDL signal, the type is an enumerated one.

VHDL code fragment:
type rxaagc_states is (INIT, WAITFORINITSD, WAITFORSD_ACT, AAGC_SP,
AAGC_COARSE, AAGC_EXTENDED, AAGC_FINE,
HBW_COUNTDOWN, RECEPTION, TRANSMIT, DUMMY1,
DUMMY2, DUMMY3, DUMMY4, DUMMY5, DUMMY6);
....
signal d_state, q_state : rxaagc_states;
....

First I tried

SystemC code fragment:
....
sc_signal< sc_lv<4> > observed_state; //16 states -> 4 bits ?!?
....
observed_state.observe_foreign_signal(path...)

Modelsim said: width mismatch between HDL SystemC signals

OK, the error message said that the bitwitdh of the HDL signal is 1(?).
Correction in the code...

Error!

I have defined an enum for the states in the SystemC wrapper with the
same states...

Error!

Please help!

Have a nice day, Peter!
 
On Jan 24, 4:04 pm, "Mr. Peterfolk" <peter.sz.kov...@gmail.com> wrote:
Hi,

I have the following problem:
I want to verify my RTL code (written in VHDL) with the golden
reference (written in C). The connection between the two model is the
SystemC (Wrapper), the simulator is the Modelsim.
I want to observe a HDL signal, the type is an enumerated one.

VHDL code fragment:
type rxaagc_states is (INIT, WAITFORINITSD, WAITFORSD_ACT, AAGC_SP,
AAGC_COARSE, AAGC_EXTENDED, AAGC_FINE,
HBW_COUNTDOWN, RECEPTION, TRANSMIT, DUMMY1,
DUMMY2, DUMMY3, DUMMY4, DUMMY5, DUMMY6);
...
signal d_state, q_state : rxaagc_states;
...

First I tried

SystemC code fragment:
...
sc_signal< sc_lv<4> > observed_state; //16 states -> 4 bits ?!?
...
observed_state.observe_foreign_signal(path...)

Modelsim said: width mismatch between HDL SystemC signals

OK, the error message said that the bitwitdh of the HDL signal is 1(?).
Correction in the code...

Error!

I have defined an enum for the states in the SystemC wrapper with the
same states...

Error!

Please help!

Have a nice day, Peter!
Click to expand...
Hello Peter

Only bit, std_logic & std_ulogic types (+ vector versions) are
supported across the SystemC/VHDL language interface.
(Have a look in the Mixed Language Simulation section of the User
Manual for full details)

Thus, you'll need some extra VHDL code to convert the enumeration into
a supported type.

Hope this helps

regards

- Nigel
 
"Mr. Peterfolk" <peter.sz.kovacs@gmail.com> wrote in message
news:1169654646.249093.311760@13g2000cwe.googlegroups.com...
Hi,

I have the following problem:
I want to verify my RTL code (written in VHDL) with the golden
reference (written in C). The connection between the two model is the
SystemC (Wrapper), the simulator is the Modelsim.
I want to observe a HDL signal, the type is an enumerated one.

VHDL code fragment:
type rxaagc_states is (INIT, WAITFORINITSD, WAITFORSD_ACT, AAGC_SP,
AAGC_COARSE, AAGC_EXTENDED, AAGC_FINE,
HBW_COUNTDOWN, RECEPTION, TRANSMIT, DUMMY1,
DUMMY2, DUMMY3, DUMMY4, DUMMY5, DUMMY6);
...
signal d_state, q_state : rxaagc_states;
...

First I tried

SystemC code fragment:
...
sc_signal< sc_lv<4> > observed_state; //16 states -> 4 bits ?!?
...
observed_state.observe_foreign_signal(path...)

Modelsim said: width mismatch between HDL SystemC signals

OK, the error message said that the bitwitdh of the HDL signal is 1(?).
Correction in the code...

Error!

I have defined an enum for the states in the SystemC wrapper with the
same states...

Error!

Please help!
Click to expand...
I don't believe you can do this, although the 6.2f User Guide is not 100%
clear on this, it does state that enum is not supported on language
boundaries. I guess you can always do it the Verilog95 way and give each
state a separate value :)

I would log this with Mentor as an enhancement request assuming of course it
is not supported.

Hans
www.ht-lab.com


Have a nice day, Peter!
Click to expand...
 
HT-Lab írta:
"Mr. Peterfolk" <peter.sz.kovacs@gmail.com> wrote in message
news:1169654646.249093.311760@13g2000cwe.googlegroups.com...
Hi,

I have the following problem:
I want to verify my RTL code (written in VHDL) with the golden
reference (written in C). The connection between the two model is the
SystemC (Wrapper), the simulator is the Modelsim.
I want to observe a HDL signal, the type is an enumerated one.

VHDL code fragment:
type rxaagc_states is (INIT, WAITFORINITSD, WAITFORSD_ACT, AAGC_SP,
AAGC_COARSE, AAGC_EXTENDED, AAGC_FINE,
HBW_COUNTDOWN, RECEPTION, TRANSMIT, DUMMY1,
DUMMY2, DUMMY3, DUMMY4, DUMMY5, DUMMY6);
...
signal d_state, q_state : rxaagc_states;
...

First I tried

SystemC code fragment:
...
sc_signal< sc_lv<4> > observed_state; //16 states -> 4 bits ?!?
...
observed_state.observe_foreign_signal(path...)

Modelsim said: width mismatch between HDL SystemC signals

OK, the error message said that the bitwitdh of the HDL signal is 1(?).
Correction in the code...

Error!

I have defined an enum for the states in the SystemC wrapper with the
same states...

Error!

Please help!

I don't believe you can do this, although the 6.2f User Guide is not 100%
clear on this, it does state that enum is not supported on language
boundaries. I guess you can always do it the Verilog95 way and give each
state a separate value :)

I would log this with Mentor as an enhancement request assuming of course it
is not supported.

Hans
www.ht-lab.com



Have a nice day, Peter!
Click to expand...
OK ! I wont waste my time to solve this!

Thanks!
 
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