bypass cap values

J

Jamie Morken

Guest
Hi all,

Is there any benefit of using a 0.1uF capacitor to bypass an IC's power
lines over using a larger value cap? For some large surface mount chips
with a lot of power pins it takes quite a few capacitors to bypass them all,
so I was wondering if there is a reason for the 0.1uF caps instead of 1uF
etc. I guess the ESR of the cap is the important variable? Would using
larger value caps smooth out more ripple on the power lines?

cheers,
Jamie Morken
 
Jamie,

I'd say the ESL (Effective Series Inductance) is more critical. This
includes the inductance of the capacitor plus the inductance of the PCB
from the cap to the pin. That's why a good rule of thumb is to have
approximately one decoupling cap per power supply pin, located as close
as possible to the pin. The exact value of the decoupling cap is usually
not critical. The typical values I use are from 0.01uF to 0.1uF with
some 0.001uF caps thrown in for devices that usually have very high
frequency content current spikes (processors, DSPs, FPGAs, etc.).

Marc

Jamie Morken wrote:
Hi all,

Is there any benefit of using a 0.1uF capacitor to bypass an IC's power
lines over using a larger value cap? For some large surface mount chips
with a lot of power pins it takes quite a few capacitors to bypass them all,
so I was wondering if there is a reason for the 0.1uF caps instead of 1uF
etc. I guess the ESR of the cap is the important variable? Would using
larger value caps smooth out more ripple on the power lines?

cheers,
Jamie Morken
Click to expand...
 
Jamie Morken wrote:
Hi all,

Is there any benefit of using a 0.1uF capacitor to bypass an IC's power
lines over using a larger value cap? For some large surface mount chips
with a lot of power pins it takes quite a few capacitors to bypass them
all,
so I was wondering if there is a reason for the 0.1uF caps instead of
1uF
etc. I guess the ESR of the cap is the important variable? Would using
larger value caps smooth out more ripple on the power lines?

cheers,
Jamie Morken
"Marc Guardiani" <marc@guardiani.com> wrote in message
news:tu66c.29370$Eg3.22104@nwrdny01.gnilink.net...
Jamie,

I'd say the ESL (Effective Series Inductance) is more critical. This
includes the inductance of the capacitor plus the inductance of the PCB
from the cap to the pin. That's why a good rule of thumb is to have
approximately one decoupling cap per power supply pin, located as close
as possible to the pin. The exact value of the decoupling cap is usually
not critical. The typical values I use are from 0.01uF to 0.1uF with
some 0.001uF caps thrown in for devices that usually have very high
frequency content current spikes (processors, DSPs, FPGAs, etc.).

Marc
Click to expand...
Well said, Marc.

ESL + C gives rise to the cap's Self-Resonant Frequency (SRF). Above SRF the
cap looks inductive. So the larger the capacitor, the lower the SRF, for 2
reasons: 1) higher C, 2) if the package gets bigger, ESL will go up, too. A
very good way of looking at this is using reactance paper.

Assume 1nH ESL for an 0805 smt 100nF cap. SRF=1/(2*pi*sqrt(LC)) = 16MHz
(|Zmin| = 0.1 Ohms or so). Below 16MHz the impedance is capacitive; above
16MHz its inductive (ie stops working as a decoupling cap). Use a leaded
cap - ESL more like 5-10nH (depends on lead length - in fact its directly
proportional to the physical area traversed by current flowing through the
cap, INCLUDING all the pcb traces - this is the physics behind Marc's
statement "located as close
as possible to the pin"), giving an SRF of 5 - 7MHz. This low ESL is one
of the great things about smt. Also, 0603 smt bits fit very nicely around
Click to expand...
SOIC8/14 opamp packages - when I do my layouts, I place the two decoupling
caps and all four -ve feedback caps directly adjacent to the SOIC14 quad
opamp pins, then lay out the circuit.....

Then use a 1uF electrolytic, which will have about 30nH ESL - SRF plummets
to about 920kHz (|Zmin| = 0.2 Ohms or so). If you plot the impedances vs
frequency, you will see that the 1uF has the lowest impedance until about
3MHz (it starts rising at 1MHz but is still lower than that of the 0.1uF smt
cap until 3MHz or so)

And of course if you try to replace say 5 0.1uF caps dotted around a (say)
TQFP64 chip with a single big cap, you have to use a much longer track to
connect the cap to all the pins, so overall ESL gets even higher......

In RF circuits, you rarely find decoupling caps above about 10nF, for
exactly this reason; it is common to see, say 10nF//100pF

On the other hand, monster decoupling caps do have their place - damping. It
is very good practice to use a few electrolytics on a pcb, and let the
electrolytics ESR damp the inevitable LC circuit present on your power
supply.

I have designed a number of smps using planar magnetics and ceramic output
caps, and invariably have wads of (carefully calculated) electrolytics to
ensure the output LC circuit is well damped - this has the added advantage
of ensuring that in the event of a short-circuit on the output being
removed, the energy stored in the output inductor 0.5LI^2 doesnt make the
output voltage rise too high.

ESR of the ceramic caps is generally pretty low - manufacturers like AVX
give you this sort of data - and so usually doesnt matter. To design a
bypass cap (rather than use a rule-of-thumb i.e. scientific wild-assed
guess), one starts with the current demand of the cct to be bypassed - Ipeak
and dt. Calculate crude dQ = Ipeak*dt, then choose C such that dV = dQ/C =
sufficiently small. Normally Ipeak is quite low, so ESR is pretty much
negligible. Mind you the old 555 timer can have around 300mA shoot-through
spikes. A pentium-type processor can have Ipeak = 20A, dt = 20ns or so - in
which case the decoupling becomes really critical. Unitrode have written a
few good app notes in this respect, like topic 1, design seminar 1100 -
fueling the megaprocessors. With nasty step changes in current like this,
designers have to take into account the entire transmission line between psu
and cpu. In fact there is a school of thought that suggests some windows
reliability problems are because cheap motherboards regularly skimp on
decoupling, which is often 10-20 tantalums, and 50-60 ceramics, mounted
directly beneath the cpu!

another word of caution: not all ceramic caps are the same. Beware Z5U/Y5V
dielectrics - these have very high relative permittivity Er, but its
dreadful with temperature AND applied DC voltage. For example a 100nF 25V
Z5U cap across a 20V supply has about 20nF of capacitance at room
temperature, and this will drop to about 4nF at 70 degrees C! Unfortunately
many people dont bother reading datasheets carefully, myself included - I
designed a 2MHz hard-switched smps using BJT's once, with just such a cap
(220nF 25V) on the +20V output. When I measured the voltage ripple, it was
about 25 times more than I expected. I checked the load current, and from
I=C*dV/dt calculated the actual C - 4nF. Say What?!? So I looked carefully
at the dielectric datasheet, then did a simple test with the cap, an LCR
bridge and a heatgun - measured results were about 100nF at 25C, 20nF at
70C, and when we applied DC bias, it plummeted......I ended up using a 100nF
X7R cap, whose voltage coefficient was small (-5% or so) and the tempco was
also small (-15% at 80C), and reduced the ripple by more than an order of
magnitude - highly counterintuitive. Since then, I routinely AVOID Z5U and
Y5V dielectrics (and indicate dielectric material in schematic)

[numbers all IIRC]
 
Subject: Re: bypass cap values
From: "Terry Given" the_domes@xtra.co.nz
Date: 3/18/2004 6:15 PM Pacific Standard Time
Message-id: <mda6c.8570$rw6.172746@news.xtra.co.nz

Jamie Morken wrote:
Hi all,

Is there any benefit of using a 0.1uF capacitor to bypass an IC's power
lines over using a larger value cap? For some large surface mount chips
with a lot of power pins it takes quite a few capacitors to bypass them
all,
so I was wondering if there is a reason for the 0.1uF caps instead of
1uF
etc. I guess the ESR of the cap is the important variable? Would using
larger value caps smooth out more ripple on the power lines?

0$Eg3.22104@nwrdny01.gnilink.net...
Jamie,

I'd say the ESL (Effective Series Inductance) is more critical. This
includes the inductance of the capacitor plus the inductance of the PCB
from the cap to the pin.
SNIP
Click to expand...

Wow Terry, thanks, what a great treatment of the subject! Well done, 5 stars,
downright enlightening, write some books the world will be better for it!

Rocky



That's why a good rule of thumb is to have
approximately one decoupling cap per power supply pin, located as close
as possible to the pin. The exact value of the decoupling cap is usually
not critical. The typical values I use are from 0.01uF to 0.1uF with
some 0.001uF caps thrown in for devices that usually have very high
frequency content current spikes (processors, DSPs, FPGAs, etc.).

Marc


Well said, Marc.

ESL + C gives rise to the cap's Self-Resonant Frequency (SRF). Above SRF the
cap looks inductive. So the larger the capacitor, the lower the SRF, for 2
reasons: 1) higher C, 2) if the package gets bigger, ESL will go up, too. A
very good way of looking at this is using reactance paper.

Assume 1nH ESL for an 0805 smt 100nF cap. SRF=1/(2*pi*sqrt(LC)) = 16MHz
(|Zmin| = 0.1 Ohms or so). Below 16MHz the impedance is capacitive; above
16MHz its inductive (ie stops working as a decoupling cap). Use a leaded
cap - ESL more like 5-10nH (depends on lead length - in fact its directly
proportional to the physical area traversed by current flowing through the
cap, INCLUDING all the pcb traces - this is the physics behind Marc's
statement "located as close
as possible to the pin"), giving an SRF of 5 - 7MHz. This low ESL is one
of the great things about smt. Also, 0603 smt bits fit very nicely around
SOIC8/14 opamp packages - when I do my layouts, I place the two decoupling
caps and all four -ve feedback caps directly adjacent to the SOIC14 quad
opamp pins, then lay out the circuit.....

Then use a 1uF electrolytic, which will have about 30nH ESL - SRF plummets
to about 920kHz (|Zmin| = 0.2 Ohms or so). If you plot the impedances vs
frequency, you will see that the 1uF has the lowest impedance until about
3MHz (it starts rising at 1MHz but is still lower than that of the 0.1uF smt
cap until 3MHz or so)

And of course if you try to replace say 5 0.1uF caps dotted around a (say)
TQFP64 chip with a single big cap, you have to use a much longer track to
connect the cap to all the pins, so overall ESL gets even higher......

In RF circuits, you rarely find decoupling caps above about 10nF, for
exactly this reason; it is common to see, say 10nF//100pF

On the other hand, monster decoupling caps do have their place - damping. It
is very good practice to use a few electrolytics on a pcb, and let the
electrolytics ESR damp the inevitable LC circuit present on your power
supply.

I have designed a number of smps using planar magnetics and ceramic output
caps, and invariably have wads of (carefully calculated) electrolytics to
ensure the output LC circuit is well damped - this has the added advantage
of ensuring that in the event of a short-circuit on the output being
removed, the energy stored in the output inductor 0.5LI^2 doesnt make the
output voltage rise too high.

ESR of the ceramic caps is generally pretty low - manufacturers like AVX
give you this sort of data - and so usually doesnt matter. To design a
bypass cap (rather than use a rule-of-thumb i.e. scientific wild-assed
guess), one starts with the current demand of the cct to be bypassed - Ipeak
and dt. Calculate crude dQ = Ipeak*dt, then choose C such that dV = dQ/C =
sufficiently small. Normally Ipeak is quite low, so ESR is pretty much
negligible. Mind you the old 555 timer can have around 300mA shoot-through
spikes. A pentium-type processor can have Ipeak = 20A, dt = 20ns or so - in
which case the decoupling becomes really critical. Unitrode have written a
few good app notes in this respect, like topic 1, design seminar 1100 -
fueling the megaprocessors. With nasty step changes in current like this,
designers have to take into account the entire transmission line between psu
and cpu. In fact there is a school of thought that suggests some windows
reliability problems are because cheap motherboards regularly skimp on
decoupling, which is often 10-20 tantalums, and 50-60 ceramics, mounted
directly beneath the cpu!

another word of caution: not all ceramic caps are the same. Beware Z5U/Y5V
dielectrics - these have very high relative permittivity Er, but its
dreadful with temperature AND applied DC voltage. For example a 100nF 25V
Z5U cap across a 20V supply has about 20nF of capacitance at room
temperature, and this will drop to about 4nF at 70 degrees C! Unfortunately
many people dont bother reading datasheets carefully, myself included - I
designed a 2MHz hard-switched smps using BJT's once, with just such a cap
(220nF 25V) on the +20V output. When I measured the voltage ripple, it was
about 25 times more than I expected. I checked the load current, and from
I=C*dV/dt calculated the actual C - 4nF. Say What?!? So I looked carefully
at the dielectric datasheet, then did a simple test with the cap, an LCR
bridge and a heatgun - measured results were about 100nF at 25C, 20nF at
70C, and when we applied DC bias, it plummeted......I ended up using a 100nF
X7R cap, whose voltage coefficient was small (-5% or so) and the tempco was
also small (-15% at 80C), and reduced the ripple by more than an order of
magnitude - highly counterintuitive. Since then, I routinely AVOID Z5U and
Y5V dielectrics (and indicate dielectric material in schematic)

[numbers all IIRC]
Click to expand...
 
"Rolavine" <rolavine@aol.com> wrote in message
news:20040319130906.25024.00001694@mb-m07.aol.com...
Subject: Re: bypass cap values
From: "Terry Given" the_domes@xtra.co.nz
Date: 3/18/2004 6:15 PM Pacific Standard Time
Message-id: <mda6c.8570$rw6.172746@news.xtra.co.nz

Jamie Morken wrote:
Hi all,

Is there any benefit of using a 0.1uF capacitor to bypass an IC's
power
lines over using a larger value cap? For some large surface mount
chips
with a lot of power pins it takes quite a few capacitors to bypass
them
all,
so I was wondering if there is a reason for the 0.1uF caps instead of
1uF
etc. I guess the ESR of the cap is the important variable? Would
using
larger value caps smooth out more ripple on the power lines?

0$Eg3.22104@nwrdny01.gnilink.net...
Jamie,

I'd say the ESL (Effective Series Inductance) is more critical. This
includes the inductance of the capacitor plus the inductance of the PCB
from the cap to the pin.
SNIP

Wow Terry, thanks, what a great treatment of the subject! Well done, 5
stars,
downright enlightening, write some books the world will be better for it!

Rocky
You're welcome. Have a look at the waffly story under Dgnd and Agnd, a few
Click to expand...
topics further down...

Cheers

Terry
 
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