Bus reduction

[Patrick]

Hello everybody,

I'm very embarassed to reduce the width of a data bus from 14 to 12 bits...

I tried this

CONV_12 : process (RAZ,clock_dac1)
begin
if RAZ = '0' then
I_12 <= (others=>'0');
Q_12 <= (others=>'0');
elsif (clock_dac1'event and clock_dac1='1') then
I_12 <= I_filt(11 downto 0);
Q_12 <= Q_filt(11 downto 0);
end if;
end process CONV_12;

But like I_filt is signed, I forgot the sign in I_12 !!

Is there any theory about this ?

Thanks...

 

[Egbert Molenkamp]

I do not know which packages you are using but in case you use numeric_std
you have a function that can be used to resize objects of type unsigned and
type signed.
In your case where the length of the signed vector is reduced from 14 to 12
bits the sign bits will be the same:
I_12 <= resize(I_filt,12);

Egbert Molenkamp

"Patrick" <patrick.melet@dmradiocom.fr> wrote in message
news:54b3002.0406070132.3144a6d1@posting.google.com...

Hello everybody,

I'm very embarassed to reduce the width of a data bus from 14 to 12
bits...

I tried this

CONV_12 : process (RAZ,clock_dac1)
begin
if RAZ = '0' then
I_12 <= (others=>'0');
Q_12 <= (others=>'0');
elsif (clock_dac1'event and clock_dac1='1') then
I_12 <= I_filt(11 downto 0);
Q_12 <= Q_filt(11 downto 0);
end if;
end process CONV_12;

But like I_filt is signed, I forgot the sign in I_12 !!

Is there any theory about this ?

Thanks...