bus pin paranth. conversion problem in .v to sch. utility

[ARAVIND]

I have a situation:
From ICFB I am importing verilog to schematic.
Its giving me the required schematic. (thats just fine and i am on what i want)

But the pins of a bus named as xyz[0] in verilog
are getting converted as xyz<0> in schematic.

Meaning [ ] the paranthesis as < > in sch.
(I have done this long back but not able to recall where ? )

Where should I set option to get the pins same as in verilog file?

 

[tritue truong]

The schematic syntax for the bus is < >. However if you produce a netlist of
that schematic. You will get back
your [ ] if you netlist is verilog. As I known you can not use [ ] for the
busses in schematic.
ttt
"ARAVIND" <arawind@yahoo.com> wrote in message
news:1d21ceeb.0404290600.580fbc87@posting.google.com...

I have a situation:
From ICFB I am importing verilog to schematic.
Its giving me the required schematic. (thats just fine and i am on what i
want)

But the pins of a bus named as xyz[0] in verilog
are getting converted as xyz<0> in schematic.

Meaning [ ] the paranthesis as < > in sch.
(I have done this long back but not able to recall where ? )

Where should I set option to get the pins same as in verilog file?