Bus interface - read, write signals

  • Thread starter valentin tihomirov
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valentin tihomirov

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Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus
transfer type designator may be whether read or write, not both
simulataneously. That is, RD and WR are mutually exclusive. Why do most bus
interfaces separate read and write signals?
 
Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus
transfer type designator may be whether read or write, not both
simulataneously. That is, RD and WR are mutually exclusive. Why do most bus
interfaces separate read and write signals?
It's probably left over from directly interfacing to ROMs or SRAMs
or Flash chips. It's easy to build small/simple logic if you
use the trailing edge of RD or WR as the clock. Think of something
like a printer port and look in your old (ancient) data books for
TTL/LS era parts.

If you only have one of RD and WR, then you also need a clock.

You might try to use CS as the clock, but the access time on ROM/RAMs
from CS is usually (much) longer than the access time from RD.
(CS typically shifts the whole chip into low power mode. It takes
a while to wake up again.)

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you missed bus idle...

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c2fed6$1rrsjl$1@ID-212430.news.uni-berlin.de...
Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The
bus
transfer type designator may be whether read or write, not both
simulataneously. That is, RD and WR are mutually exclusive. Why do most
bus
interfaces separate read and write signals?
 

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