V
valentin tihomirov
Guest
Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus
transfer type designator may be whether read or write, not both
simulataneously. That is, RD and WR are mutually exclusive. Why do most bus
interfaces separate read and write signals?
transfer type designator may be whether read or write, not both
simulataneously. That is, RD and WR are mutually exclusive. Why do most bus
interfaces separate read and write signals?