bus copying....

[GDan]

Hi,

signal a : std_logic_vector (7 downto 0)
signal b : std_logic_vector (7 downto 0)
signal c : std_logic_vector (15 downto 0)

....

c(7 downto 0) <= a(7 downto 0);
c(15 downto 8) <= b(7 downto 0);

I don't see why the compiler doesn't accept this arrangement
assertions? Basically a and b are LSB and MSB of a bus.

GD

 

[backhus]

Hi GD,
what compiler do you use?
But the problem you run into may be caused by using concurrent
assignment on the same signal. For the Compiler each concurrent
assignment is seen as a separate process. If your compiler doesn't check
the access to signal c element by element but only the whole signal you
have created a multiple driver problem. (Not really, but the way the
compiler sees it.)

You can overcome the problem by creating a single process with
sequential assignment:

AssignBus : process (a,b,)
begin
c(7 downto 0) <= a(7 downto 0);
c(15 downto 8) <= b(7 downto 0);
end process;

Have a nice simulation
Eilert

GDan schrieb:

Hi,

signal a : std_logic_vector (7 downto 0)
signal b : std_logic_vector (7 downto 0)
signal c : std_logic_vector (15 downto 0)

...

c(7 downto 0) <= a(7 downto 0);
c(15 downto 8) <= b(7 downto 0);

I don't see why the compiler doesn't accept this arrangement
assertions? Basically a and b are LSB and MSB of a bus.

GD

 

[Peter]

GDan skrev:

Hi,

signal a : std_logic_vector (7 downto 0)
signal b : std_logic_vector (7 downto 0)
signal c : std_logic_vector (15 downto 0)

...

c(7 downto 0) <= a(7 downto 0);
c(15 downto 8) <= b(7 downto 0);

I don't see why the compiler doesn't accept this arrangement
assertions? Basically a and b are LSB and MSB of a bus.

GD

Why not:
c <= b & a; --?

/Peter