bug report

I am using your 'verilog-mode.el' 2005.11.29. But I find a bug of
it.



My code has this kind of line:

output reg_wren;
output reg_rden;
assign reg_addr[7:0] = paddr[7:0];
.....


When I use the CTRL-ALT-\ to auto format it. I got this.
output reg _wren;
output reg _rden;
assign reg _addr[7:0] = paddr[7:0];


The variable name with 'reg_' is separated to to part.


I am not sure it is bug or I have not used it correctly. Can anyone
give me any hint to correct this.

Thanks in advance.

Yours
Ensoul Chi