Bug in synplify ?

I try to compile a verilog description into a specific library like
this :

add_file -verilog -lib my_lib "myfile.v"
and it doesn't work, whereas its vhdl version works perfectly :
add_file -vhdl -lib my_lib "myfile.vhdl"

i can cope with this problem if i use a shell for the verilog
description, but i have a lot a files to translate and i don't want to
spend my time for this. If i use the correct syntax, its seems there is
a bug in synplify (i tried with 7.7.1 and 8.0)

could anyone help me ?

thanks

 

it try your solution but it doesn't work.
i found a solution specific to my design (not the best solution, i
would like to resolve this problem)

thanks