V
Venkat
Guest
Folks,
I observe a curious problem on my FPGA Build on Virtex 5 FPGA and would like to understand if any of you had seen this before.
As part of SoC Emulation, I have coded my FPGA RTL with a bunch of Clock Buffers (in order to emulate Clock Gating on internal logic) which was consuming about 10 Buffers. This design build was working on the platform as expected and I wanted to free-up the BUFGs for other usage and hence eliminated the initial bunch of them by commenting them out replacing them with direct assign statements with no clock enable. Though the Build result reflected reduction in the BUFG count, I saw that the FPGA Logic is continuously held on POR and is not getting released for operations. I use the clock directly from the IO and do not use any DCM/PLL. I have used one BUFG for the Asynchronous Reset from the IO which is ANDed with another IO signal.
Did someone else come across this kind of observation?
Appreciate everyone's response.
regards,
Venkat.
I observe a curious problem on my FPGA Build on Virtex 5 FPGA and would like to understand if any of you had seen this before.
As part of SoC Emulation, I have coded my FPGA RTL with a bunch of Clock Buffers (in order to emulate Clock Gating on internal logic) which was consuming about 10 Buffers. This design build was working on the platform as expected and I wanted to free-up the BUFGs for other usage and hence eliminated the initial bunch of them by commenting them out replacing them with direct assign statements with no clock enable. Though the Build result reflected reduction in the BUFG count, I saw that the FPGA Logic is continuously held on POR and is not getting released for operations. I use the clock directly from the IO and do not use any DCM/PLL. I have used one BUFG for the Asynchronous Reset from the IO which is ANDed with another IO signal.
Did someone else come across this kind of observation?
Appreciate everyone's response.
regards,
Venkat.