BUFG, and othe calls in Verilog

So I'm calling BUFG and couple other structures, that are in the unisim
library, but ModelSim complains that it can't find BUFG and the other
structures. Now if this was VHDL I would just do a :

Library UNISIM;
use UNISIM.vcomponents.all;

but obviously I can't do that in Verilog. I tried using `library but
ModelSim didn't recognize that. I also tried using

`uselib dir=/xilinx/verilog/src/unisims libext=.v but Modelsim
complaned about that too saying it couldn't find
'/xilinx/verilog/src/unisims/work/_info'

I suppose I could rewrite my code using VHDL and use the 'Library'
call, but there's got to be a way I can use UNISIM structures when
writing in Verilog

any help is much appreciated

thank you

 

[Jim Wu]

If the unisim verilog libary is not already compiled, run "compxlib" to
compile it.

You can then add the unisim verilog library to the vsim command line.
e.g.:

vsim -t ps -L unisims_ver work.tb work.glbl

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools/





mtsuka...@gmail.com wrote:

So I'm calling BUFG and couple other structures, that are in the unisim
library, but ModelSim complains that it can't find BUFG and the other
structures. Now if this was VHDL I would just do a :

Library UNISIM;
use UNISIM.vcomponents.all;

but obviously I can't do that in Verilog. I tried using `library but
ModelSim didn't recognize that. I also tried using

`uselib dir=/xilinx/verilog/src/unisims libext=.v but Modelsim
complaned about that too saying it couldn't find
'/xilinx/verilog/src/unisims/work/_info'

I suppose I could rewrite my code using VHDL and use the 'Library'
call, but there's got to be a way I can use UNISIM structures when
writing in Verilog

any help is much appreciated

thank you

 

[RobJ]

<mtsukanov@gmail.com> wrote in message
news:1168447080.637108.272110@77g2000hsv.googlegroups.com...

So I'm calling BUFG and couple other structures, that are in the unisim
library, but ModelSim complains that it can't find BUFG and the other
structures. Now if this was VHDL I would just do a :

Library UNISIM;
use UNISIM.vcomponents.all;

but obviously I can't do that in Verilog. I tried using `library but
ModelSim didn't recognize that. I also tried using

`uselib dir=/xilinx/verilog/src/unisims libext=.v but Modelsim
complaned about that too saying it couldn't find
'/xilinx/verilog/src/unisims/work/_info'

I suppose I could rewrite my code using VHDL and use the 'Library'
call, but there's got to be a way I can use UNISIM structures when
writing in Verilog

any help is much appreciated

thank you

As Jim said, you have to compile the Xilinx unisim verilog library first.
Then you have to map the library. You can do that by placing the following
line in your modelsim.ini file:

unisims_ver = XILINX_ROOT_DIR/verilog/mti_pe/unisims_ver

In my case, XILINX_ROOT_DIR = C:/Xilinx.

Rob