Buffer Mode Ports

[Anand P Paralkar]

Hi,

I am reading a section in a book on the restrictions on buffer mode ports.
Given below are five properties of buffer mode ports. Could you please
explain the reason/rational behind them. Especially the last two:

1. If the port associated with a buffer port of a component instance is a
port of an enclosing entity, then it must be a buffer port.

2. If we associate a buffer port as an actual object with a formal port of
a component instance, the formal port must be of mode "in", "buffer" or
"linkage". It may not be of mode "out".

3. A buffer output port can only have one source. We cannot resolve a
number of sources to determine the value of a buffer port.

4. We can associate an actual signal with a buffer port of a component
instance, but that port must be the only source of the signal. We
cannot use a buffer port of a component as of a number of contributors
to a resolved signal.

Thanks,
Anand

 

[Mike Treseler]

Anand P Paralkar wrote:

Hi,

I am reading a section in a book on the restrictions on buffer mode ports.
Given below are five properties of buffer mode ports. Could you please
explain the reason/rational behind them. Especially the last two:

1. If the port associated with a buffer port of a component instance is a
port of an enclosing entity, then it must be a buffer port.

2. If we associate a buffer port as an actual object with a formal port of
a component instance, the formal port must be of mode "in", "buffer" or
"linkage". It may not be of mode "out".

3. A buffer output port can only have one source. We cannot resolve a
number of sources to determine the value of a buffer port.

4. We can associate an actual signal with a buffer port of a component
instance, but that port must be the only source of the signal. We
cannot use a buffer port of a component as of a number of contributors
to a resolved signal.

Related threads:
http://groups.google.com/groups?q=buffer+ports+hierarchy+vhdl

-- Mike Treseler