broadcasting a signal

V

valentin tihomirov

Guest
I want something like
VEC1 <= (VEC1(0)) and VEC2);

and cannot remember how. Is involving an extra signal SPLITTER <= (others =>
VEC(0)) the only solution?
 
valentin tihomirov wrote:

I want something like
VEC1 <= (VEC1(0)) and VEC2);

and cannot remember how. Is involving an extra signal SPLITTER <= (others
=> VEC(0)) the only solution?
Click to expand...
Hmmm.
"and" will mask vec1(0) with vec2
Maybe you mean that vec1(0) is a bit to shift?

vec <= newbit0 & vec(1 to n-1);

or maybe a concatination of two smaller vectors

vec1 <= vec2 & vec3;

-- Mike Treseler
 
No, I do not want to shift. In this particular case the masking is what I
want (Galios LFSR, I'm masking output bit with POLY to get taps). In
general, there can be any operation instead of "and". I have written a
function

function BIT_TO_VEC(B: std_logic; LENGTH: integer) return std_logic_vector
is
variable Result: std_logic_vector(LENGTH-1 downto 0);
begin
for I in Result'low to Result'high loop
Result(I) := B;
end loop;
return Result;
end function;

that converts a bit to vector. Usage -

UTILS.BIT_TO_VEC(REGs(0), POLY'length) and POLY

It is in reverse what reduce-class functions do. May be such a function
already exists among STD packages?
 
vec1 <= (vec1'range=>vec1(0)) and vec2;
(I assume the length of vec1 and vec2 are the same)

Egbert Molenkamp


"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> schreef in
bericht news:2rdk5aF197q2vU1@uni-berlin.de...
I want something like
VEC1 <= (VEC1(0)) and VEC2);

and cannot remember how. Is involving an extra signal SPLITTER <= (others
=
VEC(0)) the only solution?
Click to expand...
 
May be there is something similar for instantiation?

U1: entity PSA(RTL)
generic map (SIZE => SIZE)
port map (
CLK => CLK,
RESET => RESET,
ENABLE => ENABLE,
SEED => SEED,
POLY => POLY,
-- PIN => (others => '0'), -- not supported by XST
-- PIN => (SEED'range => '0'), -- cannot access psa.SIZE in this context
PIN => ZEROES, -- have to use extra signal
POUT => POUT
);

Currently, I'm using an extra signal:
constant ZEROES: std_logic_vector(SIZE-1 downto 0) := (others => '0');
 
Your function looks like the best solution to me.

for I in Result'range loop

would also work.

As you found, aggregates only
work for constants.

Declare subtypes explictly to
keep TO and DOWNTO locked down.

Default range of std_logic_vector is
natural'range which is TO not DOWNTO.

-- Mike Treseler
 
mike_treseler wrote:
Your function looks like the best solution to me.

for I in Result'range loop

would also work.

As you found, aggregates only
work for constants.
Click to expand...
Not correct, I don't think. You can use other signals, just not
vectors.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Egbert Molenkamp wrote:

vec1 <= (vec1'range=>vec1(0)) and vec2;
(I assume the length of vec1 and vec2 are the same)
Click to expand...
Becareful with this as at one point in time it did
not work on Synopsys Synthesis tools.

In VHDL-200X we are implementing an overloaded and
function that allows you to and a std_ulogic with a
std_logic_vector - so you will be able to write
it the way it is. For now you could do this function
in a separate package.

Cheers,
Jim

Egbert Molenkamp


"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> schreef in
bericht news:2rdk5aF197q2vU1@uni-berlin.de...

I want something like
VEC1 <= (VEC1(0)) and VEC2);

and cannot remember how. Is involving an extra signal SPLITTER <= (others

=

VEC(0)) the only solution?
Click to expand...

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
rickman wrote:

As you found, aggregates only
work for constants.

Not correct, I don't think. You can use other signals, just not
vectors.
Click to expand...
Sorry about that.
An aggregate is a value for an array or record type.

It can contain constant and/or variable and/or signal
elements as long as the collection matches an array
or record type in scope.

-- Mike Treseler
 
valentin tihomirov a écrit:
I want something like
VEC1 <= (VEC1(0)) and VEC2);

and cannot remember how. Is involving an extra signal SPLITTER <= (others =
VEC(0)) the only solution?
Click to expand...
I once did this by overloading the 'and' operator for std_logic and
std_logic_vector:

function "and" (l : std_ulogic; r : std_ulogic_vector) return
std_ulogic_vector is
alias rv : std_ulogic_vector (1 to r'length) is r;
variable result : std_ulogic_vector (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end "and";

(I copied the code from the std_logic_1164 package and altered it to fit
my need)

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Nicolas,
I want something like
VEC1 <= (VEC1(0)) and VEC2);

and cannot remember how. Is involving an extra signal SPLITTER <=
(others =
VEC(0)) the only solution?


I once did this by overloading the 'and' operator for std_logic and
std_logic_vector:

function "and" (l : std_ulogic; r : std_ulogic_vector) return
std_ulogic_vector is
alias rv : std_ulogic_vector (1 to r'length) is r;
variable result : std_ulogic_vector (1 to r'length);
begin
for i in result'range loop
result(i) := l and rv(i);
end loop;
return result;
end "and";

(I copied the code from the std_logic_1164 package and altered it to fit
my need)
Click to expand...
Currently it is proposed that this be added to
VHDL (for bit/bit_vector, std_ulogic/std_ulogic_vector,
std_ulogic/std_logic_vector) in the next revision of
the language.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top