Breaking out of repeat loop

[valtih1978]

I cannot find any way to do this

 

[Alan Fitch]

On 09/02/13 15:49, valtih1978 wrote:

I cannot find any way to do this

Either use IEEE 1800-2009 and use break/continue (the official Verilog

standard is now the SystemVerilog standard, IEEE 1364 is technically
obsolete), or if you use 1364, use disable. You'll have to embed the
repeat in a named block, e.g.

begin : let_me_out_of_this_damned_repeat

repeat (10)
begin
if (some_condition) disable let_me_out_of_this_damned_repeat
...
end
end

regards
Alan


--
Alan Fitch