breaking of For loop in Verilog For simulation

[Kedar P. Apte]

can we break a for loop on any condition for simulation in verilog

Rgds
Kedar

 

[Swapnajit Mittra]

Kedar P. Apte wrote:

can we break a for loop on any condition for simulation in verilog

Rgds
Kedar

Yes, in several ways which are no different from breaking
a comparable for loop in any language. Here are two:

Method 1:
---------

for (i=0; i<=999; i=i+1) begin
....
if (I_WANT_TO_STOP)
i = 1000;
end

Method 2:
---------

for (i=0; (i<=999) || (!I_WANT_TO_STOP); i=i+1) begin
....
end

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[john hong]

Kedar P. Apte wrote:

can we break a for loop on any condition for simulation in verilog

Rgds
Kedar

One way is to make the for loop a named block and use 'disable' to
break when the condition becomes true.