break statement functionality in non-blocking verilog code

[newsreader]

hi all,
I want to scan an array and get the address
of the first invalid array element.

this code does not seem to work.
always @ (posedge clock) begin
success <= 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0)) begin
array_num <= i;
success <= 'b1;
end
end
end

it works if i change non-blocking statements to blocking statements:

always @ (posedge clock) begin
success = 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0)) begin
array_num = i;
success = 'b1;
end
end
end

but the problem is I have used non-blocking statements in the
rest of my pipeline design. Interfacing non-blocking and blocking
statements is proving to be disastrous.

help ?

thanks
kiran



********************
The utmost extent of man's knowledge, is to know that he knows nothing.
********************

 

[John_H]

If you define a separate always block for this element and a different
always block for the rest of your pipeline design, it all flows. You could
also form a result outside the main always block in a combinatorial always
block and clock the result inside your pipeline design.

"newsreader" <gt4684b@mail.gatech.edu> wrote in message
newsine.SOL.4.33.0405191715210.9895-100000@acmez.gatech.edu...

hi all,
I want to scan an array and get the address
of the first invalid array element.

this code does not seem to work.
always @ (posedge clock) begin
success <= 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0)) begin
array_num <= i;
success <= 'b1;
end
end
end

it works if i change non-blocking statements to blocking statements:

always @ (posedge clock) begin
success = 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0)) begin
array_num = i;
success = 'b1;
end
end
end

but the problem is I have used non-blocking statements in the
rest of my pipeline design. Interfacing non-blocking and blocking
statements is proving to be disastrous.

help ?

thanks
kiran



********************
The utmost extent of man's knowledge, is to know that he knows nothing.
********************

 

[John Penton]

newsreader wrote:

hi all,
I want to scan an array and get the address
of the first invalid array element.

this code does not seem to work.
always @ (posedge clock) begin
success <= 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0))
begin array_num <= i;
success <= 'b1;
end
end
end

The reason for this is that the non-blocking assignments are all scheduled
to be made at the end of this code. Therefore verilog is trying to do:
sucess <= 1'b0 and: sucess <= 1'b1 at the same time. I have no idea what it
will make of that. Further, because of this, all the elements of the for
loop will see sucess == 1'b0 as TRUE.

it works if i change non-blocking statements to blocking statements:

always @ (posedge clock) begin
success = 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0))
begin array_num = i;
success = 'b1;
end
end
end

but the problem is I have used non-blocking statements in the
rest of my pipeline design. Interfacing non-blocking and blocking
statements is proving to be disastrous.

I think the problem here is that you are trying to write verilog like C - it
won't work very well. always @(posedge clock) implies a register, which you
should really assign to with a non-blocking assignment. To use the for loop
as you have tried requires blocking assignments (which imply an order to the
code). So, try separating them out:

always @(array_valid)
for (i=0; i>10; i=i+1)
if ((array_valid != 1'b1) && (success == 1'b0))
begin
next_array_num = i;
success = 1'b1;
end

always @(posedge clock)
array_num <= next_array_num;

This is untested, but I think it is an improvement.

John

--
John Penton - posting as an individual unless otherwise indicated.

 

[John Penton]

John Penton wrote:

newsreader wrote:
hi all,
I want to scan an array and get the address
of the first invalid array element.

this code does not seem to work.
always @ (posedge clock) begin
success <= 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0))
begin array_num <= i;
success <= 'b1;
end
end
end

The reason for this is that the non-blocking assignments are all
scheduled to be made at the end of this code. Therefore verilog is
trying to do: sucess <= 1'b0 and: sucess <= 1'b1 at the same time. I
have no idea what it will make of that. Further, because of this,
all the elements of the for loop will see sucess == 1'b0 as TRUE.

it works if i change non-blocking statements to blocking statements:

always @ (posedge clock) begin
success = 'b0;
for (i = 0; i > 10 ; i=i+1) begin
if ((array_valid !== 'b1) && (success == 'b0))
begin array_num = i;
success = 'b1;
end
end
end

but the problem is I have used non-blocking statements in the
rest of my pipeline design. Interfacing non-blocking and blocking
statements is proving to be disastrous.

I think the problem here is that you are trying to write verilog like
C - it won't work very well. always @(posedge clock) implies a
register, which you should really assign to with a non-blocking
assignment. To use the for loop as you have tried requires blocking
assignments (which imply an order to the code). So, try separating
them out:

always @(array_valid)

begin
success = 1'b0;

for (i=0; i>10; i=i+1)
if ((array_valid != 1'b1) && (success == 1'b0))
begin
next_array_num = i;
success = 1'b1;
end
end

always @(posedge clock)
array_num <= next_array_num;

This is untested, but I think it is an improvement.

Someone has just pointed out to me that I have omitted a line - I've added
it.

John

--
John Penton - posting as an individual unless otherwise indicated.