<break> is not declared

[rekz]

Here's part of my switch statement:

5'b01011: // COUNT LEADING ZEROES
begin
Result &lt;= 0;
for (i = 31; i &gt;= 0; i = i - 1) begin
if(Reg1 == 0)
Result &lt;= Result + 1;
else
break;
end
end

when I tried checking the syntax everything checks fine, however when
running the simulation I get the following:

ERROR:HDLCompiler:69 - "G:/Users/SingleCycleDatapath/ALU.v" Line 75:
&lt;break&gt; is not declared.
ERROR:Simulator:778 - Static elaboration of top level Verilog design
unit(s) in library work failed

why is this?

 

[Jonathan Bromley]

On Mon, 15 Mar 2010 14:05:15 -0700 (PDT), rekz wrote:

Here's part of my switch statement:

5'b01011: // COUNT LEADING ZEROES
begin
Result &lt;= 0;
for (i = 31; i &gt;= 0; i = i - 1) begin
if(Reg1 == 0)
Result &lt;= Result + 1;
else
break;
end
end

when I tried checking the syntax everything checks fine, however when
running the simulation I get the following:

ERROR:HDLCompiler:69 - "G:/Users/SingleCycleDatapath/ALU.v" Line 75:
break&gt; is not declared.
ERROR:Simulator:778 - Static elaboration of top level Verilog design
unit(s) in library work failed

why is this?

Errrm, maybe, just possibly, because "break" is not a
Verilog keyword. It exists in SystemVerilog, but you're
evidently using Xilinx and their tools don't yet even try
to support SystemVerilog.

Why did you expect "break" to work? Verilog is not C.
It is not productive to try to guess the syntax and
features of a programming language.

The curiosity about not getting a syntax error is because
Verilog cannot resolve task and function names until after
elaboration. At syntax analysis time, the Verilog compiler
thinks that "break" is the name of a user-written task
somewhere further up the design hierarchy. Of course,
when you build (elaborate) the entire design, there is
no such task and the elaboration process fails.

Find another way to code it, or learn about the "disable"
statement. And please don't guess what that does, because
I am 99.9% confident that you will guess wrongly.
--
Jonathan Bromley

 

[glen herrmannsfeldt]

rekz &lt;aditya15417@gmail.com&gt; wrote:

Here's part of my switch statement:

5'b01011: // COUNT LEADING ZEROES
begin
Result &lt;= 0;
for (i = 31; i &gt;= 0; i = i - 1) begin
if(Reg1 == 0)
Result &lt;= Result + 1;
else
break;
end
end

If you only want simulation, then maybe that is fine.

I believe, though, for synthesis it could generate 31 levels
of AND/OR logic. Maybe the logic optimization can do figure
this out and do better. Last time I did this (some years
ago) I did it as nested priority encoders. With LUT4 logic,
it is probably fastest as nested four bit priority encoders.

In any case, there is a speed/logic tradeoff that you
should consider, and that the synthesis tools might not
do the way you need it done.

-- glen

 

[rekz]

On Mar 15, 2:31 pm, glen herrmannsfeldt &lt;g...@ugcs.caltech.edu&gt; wrote:

rekz &lt;aditya15...@gmail.com&gt; wrote:
Here's part of my switch statement:
5'b01011: // COUNT LEADING ZEROES
 begin
               Result &lt;= 0;
               for (i = 31; i &gt;= 0; i = i - 1) begin
               if(Reg1 == 0)
                               Result &lt;= Result + 1;
                       else
                               break;
       end
 end

If you only want simulation, then maybe that is fine.

I believe, though, for synthesis it could generate 31 levels
of AND/OR logic.  Maybe the logic optimization can do figure
this out and do better.  Last time I did this (some years
ago) I did it as nested priority encoders.  With LUT4 logic,
it is probably fastest as nested four bit priority encoders.

In any case, there is a speed/logic tradeoff that you
should consider, and that the synthesis tools might not
do the way you need it done.

-- glen

so if there's no way of doing break then what is the alternative of
exiting a for loop in verilog?

 

[glen herrmannsfeldt]

rekz &lt;aditya15417@gmail.com&gt; wrote:
(snip)

so if there's no way of doing break then what is the alternative of
exiting a for loop in verilog?

If you think in terms of hardware, exiting a loop doesn't have
any meaning.

A loop instatiates a specific number of logic block, depending
in the loop limit.

You might try adding zero in the else case, in which case the
synthesizer has logic to generate either way that the if goes.
(Add either zero or one to the accumulated sum.)

That is what it would have to do with break, if it allowed it.
The result, then, is 31 adders, each with an input of 0 or 1,
chained together. I would expect logic minimization to figure
out that the earlier adders are not full width.

-- glen