Branch prediction

[Guy Montag]

Hi!

I'm a student and I'm looking for some info about Branch prediction vhdl
description. Someone could help me?

Thanks

 

[valentin tihomirov]

There are 3 levels of description. "Branch prediction" is an algorithm. At
algorithmic level you should know that there must be a bit-flag accompanying
every branch instruction. At the next (lower) level, you should define the
architecture. Whether it will be a cache mapping instruction addr => flag
(seems very expensive) or you'll accompany each instruction in the
instruction cache with a single bit or something else. Then you'll find many
people in this newsgroup aiding you to describe the schema in VHDL.

;-)

 

[Guy Montag]

Thanks for your answer. I need exactly a Branch prediction algorithm,
have you some links which I could refer to?

valentin tihomirov ha scritto:

There are 3 levels of description. "Branch prediction" is an algorithm. At
algorithmic level you should know that there must be a bit-flag accompanying
every branch instruction. At the next (lower) level, you should define the
architecture. Whether it will be a cache mapping instruction addr => flag
(seems very expensive) or you'll accompany each instruction in the
instruction cache with a single bit or something else. Then you'll find many
people in this newsgroup aiding you to describe the schema in VHDL.

;-)