branch prediction

[vittal]

Hi,
I am working on different branch prediction techniques for a
processor.
any help on this would be appreciated.
Thanks,
Vittal

 

[alan]

On Apr 16, 4:38 pm, "vittal" <vittal.pa...@gmail.com> wrote:

Hi,
I am working on different branch prediction techniques for a
processor.
any help on this would be appreciated.
Thanks,
Vittal
Here's the simplest implementation:

In your instruction opcode, add a single bit for "branch predict".
Really. That's the simplest implementation - pass it to the compiler,
which is, believe me, a lot easier to design. In fact, if you'll be
using GCC, I believe it already has support for such a bit- you just
need to specify it in the processor description file. Savvy Assembly
language programmers will also appreciate this bit.

The slightly less simple implementation that won't modify your
instruction set is to use a small SRAM buffer (or even vector of FF's,
if you're rich). Let us say this SRAM buffer has N bits (bits, mind
you). When you encounter a branch instruction at address A, get A
modulo N. Index that bit. Assume that this bit is correct. If it's
1, predict a branch taken, otherwise predict a branch not taken. When
the branch is actually executed, write a 1 to that bit if it's taken
and a 0 if it's not taken. This is the canonical implementation -
everything above this is just this with lots and lots of gravy.

And always, always be prepared for a pipeline flush. Prediction, by
its very nature, is uncertain. Refinements allow you to detect
whether it's guessing or not, but at some point you still have to
guess.