BPSK on VHDL (warning - VHDL newbie)

P

pygmalion

Guest
Hello,

I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.

Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?

Thanks and regards,

Abhishek
 
If you have some algorithm for these stuff, implement a vhdl code will
be easy. People of this list can give lots of helpfull information
using the language, syntax and digital logic. I always answer the most
newbie question with an appropriate reading and knowledge base needed.

I must say: get the hands on it.

Regards,

Ricardo

pygmalion escreveu:

Hello,

I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.

Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?

Thanks and regards,

Abhishek
Click to expand...
 
On 22 Jun 2006 05:10:30 -0700, "pygmalion" <abhisheknag@gmail.com>
wrote:

Hello,

I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.

Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?
Click to expand...

Is it truly BPSK, i.e. two possible phases 180 degrees apart? If so,
then you can easily spot a phase *transition* by detecting zero-
crossings of both I and Q at roughly the same time. The much
slower phase changes caused by carrier frequency errors will
give rise to zero-crossings of only one of I,Q; and it will
always be the smaller-amplitude component that will change
sign, while the larger-amplitude component stays roughly
constant. A true BPSK transition will have a zero-crossing
(polarity reversal) of the component with *larger* amplitude.

Once you have the phase transitions, you don't really need to
compensate for frequency errors or phase offsets. And I
imagine you will be able to put the data stream back together
from the transitions without too much trouble.

However, once you can tell the difference between phase
drift and phase transitions, it should be easy enough to
extract the phase drift and use it as feedback to the
demodulator. You may wish to Google for "Costas loop"
and "carrier tracking loop" in this context.

To get further I would want to see more detail of the
modulation scheme and data encoding in your system,
as well as details of the carrier, sampling and symbol rates.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
In message <nd8l929pfb1oodrvs7v6vihbv4snv6735g@4ax.com>
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:

To get further I would want to see more detail of the
modulation scheme and data encoding in your system,
as well as details of the carrier, sampling and symbol rates.
Click to expand...
.... and their tolerances.

Dave
 
Hello Jonathan,

I am going to try to code this idea to VHDL. As you've correctly
assumed, the modulation is simple BPSK, so, your idea should work.
There is Viterbi decoding after the demodulation, but, I've been able
to implement that successfully.

Dave,

The system uses convolutional encoding. Symbol rate is 8 Mbps. There is
an Analog Devices AD6654 ADC before the FPGA which does the IF to IQ
conversion to return IQ data at desired symbol rates.

Thanks and regards,

Abhishek


Dave Higton wrote:
In message <nd8l929pfb1oodrvs7v6vihbv4snv6735g@4ax.com
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:

To get further I would want to see more detail of the
modulation scheme and data encoding in your system,
as well as details of the carrier, sampling and symbol rates.

... and their tolerances.

Dave
Click to expand...
 
hii
i have algorithem for phase estimation but it requires reference data
what we r transmitting so can u tell me some alogorithm that dosnt use
reference data for phase and frequency estimation for bpsk modulation.
regards
sandeep
Jonathan Bromley wrote:
On 22 Jun 2006 05:10:30 -0700, "pygmalion" <abhisheknag@gmail.com
wrote:

Hello,

I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.

Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?


Is it truly BPSK, i.e. two possible phases 180 degrees apart? If so,
then you can easily spot a phase *transition* by detecting zero-
crossings of both I and Q at roughly the same time. The much
slower phase changes caused by carrier frequency errors will
give rise to zero-crossings of only one of I,Q; and it will
always be the smaller-amplitude component that will change
sign, while the larger-amplitude component stays roughly
constant. A true BPSK transition will have a zero-crossing
(polarity reversal) of the component with *larger* amplitude.

Once you have the phase transitions, you don't really need to
compensate for frequency errors or phase offsets. And I
imagine you will be able to put the data stream back together
from the transitions without too much trouble.

However, once you can tell the difference between phase
drift and phase transitions, it should be easy enough to
extract the phase drift and use it as feedback to the
demodulator. You may wish to Google for "Costas loop"
and "carrier tracking loop" in this context.

To get further I would want to see more detail of the
modulation scheme and data encoding in your system,
as well as details of the carrier, sampling and symbol rates.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
In message <1151056503.984277.148070@p79g2000cwp.googlegroups.com>
"pygmalion" <abhisheknag@gmail.com> wrote:

Dave,

The system uses convolutional encoding. Symbol rate is 8 Mbps.
Click to expand...
*Nominally* 8 Mbps.

I've seen so many systems malfunction because the designer(s) didn't
think that the signal is *never* that frequency. The only argument
is about the size of the error.

I'm not saying you've made the error; I'm just making sure you don't!

Dave
 
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