Y
Yves Tchapda
Guest
Hi all,
Has anyone used BSD Architect to automate the boundary scan on an
ASIC. If so, how have you managed to apply timing constraints on the
boundary scan section (BS cell registers, instruction registers and
other internal registers)?
The clocking is so convoluted, with some registers clocked by clockdr
derived from the the shiftDR state (when data is being shifted) and
other registers clocked by updatedr derived from the update state.
These clocks are further gated by signals from the instruction
decoder. To make it worse, the update registers (clocked by a gated
version of updatedr) are connected to the shift registers clocked by
the a gated version of clockdr!
Any advice will be appreciated
Cheers
Yves
Has anyone used BSD Architect to automate the boundary scan on an
ASIC. If so, how have you managed to apply timing constraints on the
boundary scan section (BS cell registers, instruction registers and
other internal registers)?
The clocking is so convoluted, with some registers clocked by clockdr
derived from the the shiftDR state (when data is being shifted) and
other registers clocked by updatedr derived from the update state.
These clocks are further gated by signals from the instruction
decoder. To make it worse, the update registers (clocked by a gated
version of updatedr) are connected to the shift registers clocked by
the a gated version of clockdr!
Any advice will be appreciated
Cheers
Yves