both edge triggered and level triggered signal

[papu]

Hi,

I need to place both edge triggered and level triggered signal in the
sensitibity list in "always @()" statements. Verilog allows it. My
program compiles without any error in Modelsim.

I was trying to synthesize the same in Xlinix webpack, but it
wouldn't let me do it. On its website they have mentioned that both
level triggered and edge triggered aren't allowed. Is there anyway to
get around it or does any other systhesis tool let you do that? Thank
you in advance.

Papu.

 

[John_H]

Xilinx Webpack is concerned with Synthesizable Verilog which is a subset of
Simulatable Verilog.
Since Webpack targets hardware, you have to fit the logic within the
constraints of what the hardware can handle.

While you may consider a reset to be a level sensitive signal, I believe
Verilog treats a non-edge signal in the sensitivity list as "posedge or
negedge" not "pos." Any transition on the signal causes the simulator to
enter the block.

If you had a simple reset, the construct

always @(posedge clock or reset)
if( reset ) Val <= 1'b0;
else Val <= input;

would enter both on the posedge of reset which is what is desired but it
will also enter on the negedge of reset. Since the if(reset) evaluates to
false on the negedge, the Val <= input *will* be performed by the simulator.
To get the proper reset, the entry needs to be *only* on the rising edge, so

always @(posedge clock or posedge reset)
if( reset ) Val <= 1'b0;
else Val <= input;

results in the reset only when the signal asserts (or the posedge clock
comes along while still asserted) but exiting the reset leaves the register
alone.

If you're trying to accomplish more than the simple set/reset, consider how
the hardware *can* implement what you want to do. Is your construct able to
be realized with the existing transistors in your target device?


"papu" <prachar@gmail.com> wrote in message
news:1095955221.060749.137750@k17g2000odb.googlegroups.com...

Hi,

I need to place both edge triggered and level triggered signal in the
sensitibity list in "always @()" statements. Verilog allows it. My
program compiles without any error in Modelsim.

I was trying to synthesize the same in Xlinix webpack, but it
wouldn't let me do it. On its website they have mentioned that both
level triggered and edge triggered aren't allowed. Is there anyway to
get around it or does any other systhesis tool let you do that? Thank
you in advance.

Papu.

 

[glen herrmannsfeldt]

papu wrote:

I need to place both edge triggered and level triggered signal in the
sensitibity list in "always @()" statements. Verilog allows it. My
program compiles without any error in Modelsim.

In behavioral verilog, the sensitivity list is needed even for
non-register logic. Note also that the reg declaration does
not necessarily signify a register. Consider

reg x;
always @(a or b) x=a+b;

since x is reg its value won't change unless an assignment
is executed to change it. In x=a+b, x can only change
if a or b changes. Now, consider

reg x;
always @(clock) x=a+b;

Technically this should synthesize a register that latches
the value of a or b on either the rising edge or falling edge,
latching the current value of a+b. As such registers are rare,
it is unlikely to synthesize, but it can be simulated. Consider

reg x;
always @(clock or a or b) if(clock) x=a+b;

This could synthesize a transparent latch, with a+b
as its input. I believe some will synthesize this using
logic resources instead of FF's.

Note, though, that changes to the sensitivity list can have
a large effect on the meaning of a statement. There is also

wire x;
assign x=a+b;

in structural verilog, with no ambiguity in meaning.

-- glen