A
Atif
Guest
I want to implement Booth's algorithm in verilog for multiplying two
four bit numbers with an output of 8 bits.
I have designed two modules addsub and shift which works fine
indivisually. But when I use them in my mul module (that is a module
to implement booth's algo). I've to use them inside the procedural
blocks to add/sub or shift the numbers to implement the booth's algo.
But I cannot instantiate any module inside a procedural block.
module addsub(out, a, b);
....
endmodule
module shift(out, a, b);
....
endmodule
module mul(out, a, b);
....
initial
begin
if(out[0]<invbit)
addsub myadd(out,..,.. );
end
endmodule
How can I solve this problem?
Regards
Atif Nadeem
four bit numbers with an output of 8 bits.
I have designed two modules addsub and shift which works fine
indivisually. But when I use them in my mul module (that is a module
to implement booth's algo). I've to use them inside the procedural
blocks to add/sub or shift the numbers to implement the booth's algo.
But I cannot instantiate any module inside a procedural block.
module addsub(out, a, b);
....
endmodule
module shift(out, a, b);
....
endmodule
module mul(out, a, b);
....
initial
begin
if(out[0]<invbit)
addsub myadd(out,..,.. );
end
endmodule
How can I solve this problem?
Regards
Atif Nadeem